Hallo all, I am writing interputs for a fpga and dsp need to interact with a dual port memory shared dpram control in vhdl. I have External IOs coming from the SPI bus on oneside to the fpag to be communicated with dsp and on the otherhand have a camera to the to the dsp. So my intrups are like Havinf a FIFO being reset after everytime a FSM reads and writes the interrpts with dsp. Now my problem is 1) I want to enable some particular interupts at a time and disable the others. 2)When make a masking with logical XOR function the other interupts coming from UART goes for a timeout. 3)When this is done the camera gets the signal but cant be controlled. I use the following algorithm to deal with all asynchron inputs: 1. In event2reg_array_proc: save all inputs to parallel buffers “fifo_data_input_array”, each input(flag) should be put into separate buffer. 2. In reg_array2fifo_proc2: read each buffer serially and save them in a fifo “fifo320x32”. 3. In main FSM read the output from fifo and do the suitable processing, each cycle read out only one value, it should be one flag. If you get some flags which remains in register even after processing, the reason can be: 1. In event2reg_array_proc: and reg_array2fifo_proc2:, if one flag (in buffer) has been written in the fifo, it should be cleared from the buffer. I use the “fifo_cnt” to control this. You can use simulation to check. 2. Line Camera sends the FRAME_VALID signal as same as the LINE_VALID signal, so you can get a lot of CAM2DSP_FRAME_SYNC_FLAG with Line Camera. So can any one suggest any algorithm to enable particular interupts while the the camera is still communicating with DSP.
Guest
#2917341
I would like to put the question other way round. How to enable a particular interrupt in a FSM with case statement, and the interrupts are coming as Std_logic_vector? How to enable or disable a flag in a 64 bit in a FSM??
Guest
#2917369
& bitmask
Guest
#2917402
What do you mean with "interrupt" anyway? A FPGA has no interrupts...
Guest
#2917444
Interurpt is to enable or disable a particular flag
Guest
#2917564
Seems like you have no idea what you're talking about
Guest
#2917590
An interrupt would be something that interrupts something, like the sequential program flow on a CPU. A state machine is something that resides in a certain state unless there are conditons which make it go into a different state. You cannot interrupt a state, as a consequence you cannot interrupt a state machine. All you can do is change a condition, so the state machine would switch into a different state.
Guest
#2917771
A SPI bus has to send the UART and SPI signal to the DSP from the FPGA memory thats what i mean by interrupts. On the otherhand a camera also has to get Camera link signals from the DSP from the FPGA. For his i have a dualport ram with one side fpga and the other side the DSP. I have used a FIFO to read these signal and send them to the FPGA. Here i use a simple state machine to write the flags status, write and read the flags. Now my question is to read and write some flags instead of all of them. For this used the AND and XOR operation on this to mask,but the problem is it being a 64 bit vector and the uart goes for a timeout for which the camera resposnse stops after get intial 2 to 3 packets as they get masked. So i want to read some values and keep off the others.
Guest
#2917799
I never get your point. A SPI bus is an interrupt and interrupts a state machine but all you want to do is to mask some bits but the UART goes into timeout? I want to build a space ship - where do I start and how do I drill a hole into wood?
Guest
#2918876
Use DMA instead of Interrupt! This will also fix your UART problems.
Guest
#2918960
Thanks Lance....i think you got what i was trying to say...I will try to do will DMA in the DSP.
Guest
#2919072
Not in the DSP, stupid, in the FPGA of course!
Guest
#2919087
Maybe his FPGA does not have DMA. @vikram: does your FPGA has inbuilt DMA?
Guest
#2919096
My FPGA doesnt have a DMA on it. its Lattice ECP2..
Guest
#2919148
Hard luck
Guest
#2919152
I am downloading a DMA IP which has a wishbone controller in it.
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