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Forum: FPGA, VHDL & Verilog Error in simple code


von tino t. (tino09)


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Hello everyone, I am a newbie in VHDL, Im programming a code for 
simulating a T flip flop but all I get are errors.. Right now my code is 
not supossed to do nothing but giving the value '1' to q_temp but Im 
getting this error in line 47 and I dont know why, can anyone help me 
please?

Line 47. Variable 'q_temp' q_temp is at left hand side of signal 
assignment statement.
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entity TFF2 is
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    Port ( T : in  STD_LOGIC;
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           CLK : in  STD_LOGIC;
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           Q : out  STD_LOGIC;
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           notQ : out  STD_LOGIC);
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end TFF2;
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architecture Behavioral of TFF2 is
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begin
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  Tff: process (CLK, T) is
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    variable q_temp: std_logic :='0';
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      begin
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       if (clk'event and CLK = '1' and T = '1') then 
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      q_temp <= '1';  --LINE 47
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     end if;
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  end process;
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  --q_next<='1';  
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  --q_past <= '1';
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 -- Q <= q_temp;
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  --Q <= '1';
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end Behavioral;

von Lothar M. (lkmiller) (Moderator)


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Try this in line 47:
   q_temp := '1';

And read about the differences between variables and signals.

von tino t. (tino09)


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Thank you, thank fixed it. I still have a lot to learn :)

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