Hi, Can we assign constant or values directly to ports during component instantiation. Code Snippet : fir_1 : fir_d port map ( clk => clk, ctl_R => "0110111000000001", -- input port of 16 bits . . . ); If we assign, will it be trimmed during synthesis? Any other method to pass values to ports. Thanks
When you apply constant values to a port, then the synthesis tool will optimize it (if enabled). FPGA synthesis tools have optimization enabled by default, ASIC synhtesis tools not.
It is also possible to use "generic" and "generic map"
The constraint with the above code is that, I have to pass values through ports only. To pass values to ports, I tried another method using ROM. Code Snippet : -------------------------------------------------------------------- entity app is port ( clk : in std_logic; rst : in std_logic; ce : in std_logic; a0 : out std_logic_vector(15 downto 0); a1 : out std_logic_vector(15 downto 0) ); end app; architecture Behavioral of app is component counter is generic ( width : integer := 10; limit : integer := 512 ); port(clk, clr, ce : in std_logic; q : out std_logic_vector((width-1) downto 0); q_valid : out std_logic); end component; component rom_file is generic ( width : integer := 10; limit : integer := 512; FileName : string := "" ); port ( clka : in std_logic; ena : in std_logic; addra : in std_logic_vector((width-1) downto 0); doa : out std_logic_vector(15 downto 0) ); end component rom_file; component reg is generic ( Width : integer := 16 -- port width ); port ( clk : in std_logic; ce : in std_logic; rst : in std_logic; d : in std_logic_vector((Width-1) downto 0); q : out std_logic_vector((Width-1) downto 0) ); end component reg; signal s_addr : std_logic_vector(3 downto 0); signal s_data : std_logic_vector(15 downto 0); type reg_array is array (0 to 9) of std_logic_vector(15 downto 0); signal reg_data : reg_array; begin cntr1 : counter generic map ( width => 4, limit => 10 ) port map ( clk => clk, clr => rst, ce => ce, q => s_addr, q_valid => open ); rom_fir : rom_file generic map ( width => 4, limit => 10, FileName => "./rom/fir_p.dat" ) port map ( clka => clk, ena => '1', addra => s_addr, doa => s_data ); --generate_data_out : for i in 0 to 9 generate process(clk) begin if(clk'event and clk = '1') then for i in 0 to 9 loop reg_data(i) <= s_data; end loop; end if; end process; --end generate generate_data_out; reg_val1 : reg generic map ( width => 16 ) port map ( clk => clk, rst => rst, ce => ce, d => reg_data (0), q => a0 ); reg_val2 : reg generic map ( width => 16 ) port map ( clk => clk, rst => rst, ce => ce, d => reg_data (1), q => a1 ); end behavioral; --------------------------------------------------------------- In this method, I'm trying to store each value of ROM into separate registers. Suppose ROM contains {0001, 00AD, 987B,...}, then reg 1 should contain the value 0001 only, reg 2 should contain 00AD only and so on. For counter and ROM, Xilinx HDL codes are used. In entity app, only two output ports are mentioned for simplicity. But the above code is storing all the values of ROM in each registers. Kindly guide me. Thanks
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.