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Forum: FPGA, VHDL & Verilog car taillights


car taillights
von Dfd D. (dfd_d)

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I am trying to do a T-Bird tail light function using VHDL. I have been 
able to get the emergency (Hazard) and Left and right turn to work  and 
brake but can not get the when brake light and the lights in the 
direction of the turn function as before, the lights opposite the tail 
lights are all on

below is my code

so what i want to do is "When the brakes are on, and

when the hazard is on, it takes precedence and the tail lights all blink 
as before got this to work.
when the left or right turn signal is on, the lights in the direction of 
the turn function as before, the lights opposite the tail lights are all 
on. can't get this to work

 when the brakes are on and the hazard and left or right are not, the 
tail lights are all on. got this to work.

1
library IEEE;

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use IEEE.std_logic_1164.all;

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ENTITY tbird_lc is

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  GENERIC(DIVISOR : positive := 10000000);

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  PORT(clk           : IN  std_logic;

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       rst           : IN  std_logic;

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       left          : IN std_logic;

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       right         : IN std_logic;

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       haz           : in std_logic;

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     brake         : IN std_logic; 

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       left_tail_lt  : OUT std_logic_vector(3 downto 1);

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       right_tail_lt : OUT std_logic_vector(1 to 3));

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END tbird_lc;

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ARCHITECTURE behavior OF tbird_lc IS

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  TYPE state_type IS (IDLE, LR3, L1, L2, L3, R1, R2, R3,LB,LB1,LB2,LB3);

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  SIGNAL present_state, next_state : state_type;

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  CONSTANT leftoff : std_logic_vector(3 downto 1) := "000";

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  CONSTANT left1on : std_logic_vector(3 downto 1) := "001";

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  CONSTANT left2on : std_logic_vector(3 downto 1) := "011"; 

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  CONSTANT left3on : std_logic_vector(3 downto 1) := "111";

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  CONSTANT rightoff : std_logic_vector(3 downto 1) := "000";

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  CONSTANT right1on : std_logic_vector(3 downto 1) := "100";

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  CONSTANT right2on : std_logic_vector(3 downto 1) := "110";

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  CONSTANT right3on : std_logic_vector(3 downto 1) := "111";

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  signal sclk: std_logic;

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BEGIN

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 DIVIDER : entity work.clock_divider(behavior)

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generic map (DIVISOR => DIVISOR)

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port map (clk => clk, rst => rst, q => sclk);

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 clocked : PROCESS(sclk,rst)

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   BEGIN

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     IF(rst='1') THEN 

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       present_state <= idle;

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    ELSIF(rising_edge(sclk)) THEN

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      present_state <= next_state;

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    END IF;  

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 END PROCESS clocked;

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 nextstate : PROCESS(present_state,left,right,haz, brake)

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  BEGIN

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     CASE present_state IS

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       WHEN idle =>

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         IF(haz = '1' OR(brake='1' and haz='1')OR (left = '1' AND right = '1')) THEN

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           next_state <= LR3;

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         ELSIF(left = '1') THEN

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           next_state <= L1;

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      ELSIF (left='1' and brake='1') THEN  --trying to make another state for left and brake

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        next_state<=LB1;          

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         ELSIF(right = '1') THEN

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           next_state <= R1;

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      ELSIF(brake='1' and haz='0' and left='0' and right='0')THEN

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         next_state<=LR3;  

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         ELSE

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           next_state <= idle;

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         END IF;

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       WHEN LR3 =>

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       IF(brake='1' and haz='0' and left='0' and right='0') THEN

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        next_state<=LR3; 

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      else

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         next_state <= idle;

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       END IF; 

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       WHEN L1 =>

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         IF(haz = '1' or (brake='1' and haz='1') ) THEN

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           next_state <= LR3;

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         ELSE

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           next_state <= L2;

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         END IF;

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       WHEN L2 =>

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         IF(haz = '1' or (brake='1' and haz='1') ) THEN

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           next_state <= LR3;

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         ELSE

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           next_state <= L3;

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         END IF;

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       WHEN L3 =>

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         next_state <= idle;

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       WHEN R1 =>

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         IF(haz = '1' or (brake='1' and haz='1')) THEN

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           next_state <= LR3;

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         ELSE

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           next_state <= R2;

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         END IF;

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       WHEN R2 =>

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         IF(haz = '1' or (brake='1' and haz='1')) THEN

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           next_state <= LR3;

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         ELSE

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           next_state <= LB;

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         END IF;

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       WHEN R3 =>

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         next_state <= idle;

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     WHEN LB1 =>        --next state for left and brake 

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       IF (left='1' and brake='1') THEN 

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        next_state<=LB2; 

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         else 

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           next_state<=LB;     

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      END IF; 

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     WHEN LB2=>

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       IF (left='1' and brake='1') THEN 

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        next_state<=LB3; 

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      ELSE

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        next_state<=LB; 

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      END IF; 

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     WHEN LB3 =>

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       next_state<= idle; 

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       WHEN LB => 

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           next_state<=LB;      

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    END CASE;

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  END PROCESS nextstate;

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  output : PROCESS(present_state)

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   BEGIN

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     CASE present_state IS

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       WHEN idle =>

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         left_tail_lt <= leftoff;

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         right_tail_lt <= rightoff;

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       WHEN LR3 =>

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         left_tail_lt <= left3on;

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         right_tail_lt <= right3on;

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       WHEN L1 =>

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         left_tail_lt <= left1on;

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         right_tail_lt <= rightoff;

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       WHEN L2 =>

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         left_tail_lt <= left2on;

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         right_tail_lt <= rightoff;

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       WHEN L3 =>

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         left_tail_lt <= left3on;

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         right_tail_lt <= rightoff;

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       WHEN R1 =>

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         left_tail_lt <= leftoff;

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         right_tail_lt <= right1on;

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       WHEN R2 =>

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         left_tail_lt <= leftoff;

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         right_tail_lt <= right2on;

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       WHEN R3 =>

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         left_tail_lt <= leftoff;

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         right_tail_lt <= right3on;

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      WHEN LB1 =>         --trying to do left and brake but working

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         left_tail_lt <= left1on;

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         right_tail_lt <= right3on;

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       WHEN LB2 =>

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         left_tail_lt <= left2on;

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         right_tail_lt <= right3on;

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       WHEN LB3 =>

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         left_tail_lt <= left3on;

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         right_tail_lt <= right3on;

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    WHEN LB => 

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      right_tail_lt <=right3on; 

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      left_tail_lt<=leftoff; 

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     END CASE;

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 END PROCESS output;

155
 

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END ARCHITECTURE behavior;


  


  




  

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    Re: car taillights
  


  

    

      von
      
        P. K.
        (pek)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Why do you one signle state machine, that codes everything?

You have a number of lights that are independant, so you shouldn't code 
them into one big state machine, creating dependancies where they don't 
really exist.

I doubt whether you even need a state machine. Maybe it is just enough 
to register the inputs for synchronisation and if required debounce them 
and afterwards do a pure combinational assignment. e.g:

1
brake_left <= '1'   when brake_registered_debounced = '1' else

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              '0';

3
dir_left   <= blink when left_registered_debounced = '1' or

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                         haz_registered_debounced = '1' else

5
              '0';

...

"blink" is an independantly generated (ever running) blinking signal 
running at your desired speed.

  


  




  

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    Re: car taillights
  


  

    

      von
      
        elver galarga (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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comeme la v3rg4

  


  




  

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