module latch(output reg q,input d,input clk);
  always
  begin
  wait (clk) #100 q=d;
  end
endmodule
module simlat;
  reg D,CLK;
  wire Q;
  initial D=1'b1;
  initial CLK=0'b1;
  latch l1(Q,D,CLK);
  //always #10 CLK=~CLK;//if this is included my simulator hangs 
completely
  initial #16 D=~D;
  initial #200 $finish;
endmodule

//without that statement prgram works just fine. please tell me why??
// thanks in advance.