Forum: FPGA, VHDL & Verilog level sensitive timing control

Author: neha s. (neha_s)
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module latch(output reg q,input d,input clk);
  wait (clk) #100 q=d;
module simlat;
  reg D,CLK;
  wire Q;
  initial D=1'b1;
  initial CLK=0'b1;
  latch l1(Q,D,CLK);
  //always #10 CLK=~CLK;//if this is included my simulator hangs 
  initial #16 D=~D;
  initial #200 $finish;

//without that statement prgram works just fine. please tell me why??
// thanks in advance.

Author: wait? (Guest)
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You can't synthesize a wait... try with

always @(posedge clk)

Author: jojo (Guest)
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always begin

#10 CLK=~CLK;


maybe helps?


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