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Forum: FPGA, VHDL & Verilog synchronous counter using jk flipflop


von neha s. (neha_s)


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module sync4coun(output [3:0]qx,input clrx,input clkx, input enx);
  wire p,t,n;
  wire [3:0]qbar;
  assign p=enx&qx[1],
         t=p&qx[2],
         n=t&qx[3];
  jk j1(qx[0],qbar[0],en,en,clrx,clkx);
  jk j2(qx[1],qbar[1],p,p,clrx,clkx);
  jk j3(qx[2],qbar[2],t,t,clrx,clkx);
  jk j4(qx[3],qbar[3],n,n,clrx,clkx);
endmodule
module jk(output q,output qbar,input j,input k, input clr,input clk);
  wire a,b,y,ybar,c,d,cbar;
  assign  c=!c,
          a=!(j&qbar&clk&clr),
          b=!(k&q&clk),
          y=!(a&ybar),
          ybar=!(clr&b&y),
          c=!(y&cbar),
          d=!(ybar&cbar),
          q=!(c&qbar),
          qbar=!(d&clr&q);
endmodule
module s5;
  reg CLR,CLK,EN;
  wire [3:0]Q;
  assign Q=4'b0000;
  initial
  begin
    $monitor($time,"count q = %b clr = %b",Q[3:0],CLR);
  end
  sync4coun s1(Q,CLK,CLR,EN);
  initial
  begin
    CLR=1'b1;
    EN=1'b1;
    #10 CLR=1'b0;
    #50 CLR=1'b1;
    EN=1'b1;
    #30 CLR=1'b0;
  end
  initial
  begin
    CLK=1'b0;
    forever #5 CLK=~CLK;
  end
  initial
  begin
    #200 $finish;
  end
endmodule
/////
/////q in simulator shows only value x.
///i am a beginner in verilog. please help me out.
////thanks in advance

von Lothar M. (lkmiller) (Moderator)


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> q in simulator shows only value x.
How does the testbench look like?
> i am a beginner in verilog.
Me too. But I'm well known to VHDL. And I'm missing a test bench.
> please help me out.
http://www.asic-world.com/verilog/art_testbench_writing.html

von T. M. (xgcfx)


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I think module s5 is the test bench. But the whole code is very hard to 
read. I'm not shure if it is possible to describe a JK-FF in a way like 
module jk does. Maybe, you should look after  the state of the internal 
variables of module jk in simulation. If their state is right or false.

von neha s. (neha_s)


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s4 is the test bench.
instead of c=!c, cbar=!clk will used. the code for jk module is for a 
master slave jk flipflop. with the above change now the value for q 
stays 4'b0000 and if i remove the statement of initializing assign 
q=4'b0000, i again get 4'bxxxx for q. please help.

von bko (Guest)


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I done want to debug a gatelevel JK-flilflop so I give
just some recommendations to yout code:

If you have an verilog-2001 simulator then the first
thing you should add on the top of your verilog code
is this:
 `default_nettype none
It errors implcite connections, which are are a major source of trouble 
in verilog, see discussed here:
http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/47017a6917653f62

A verilog-2001 capable simulator for free would be icarus:
http://iverilog.icarus.com/

If possible you should avoid connection by position as
you do here:
 sync4coun s1(Q,CLK,CLR,EN);

Connection by Name avoids trouble e.g:
  sync4coun s1(.qx(Q),
               .clkx(CLK),
               .clrx(CLR),
               .enx(EN));

see:  http://www.asic-world.com/verilog/syntax2.html

In verilog cou can create a waveform with that command
in your code:
begin
    $dumpfile("show_vcd.vcd"); // waveform filename
    $dumpvars(4);              // how deep to dump

    $monitor($time,"count q = %b clr = %b",Q[3:0],CLR);
  end

Then you should debug your verilog code with and waveform
 viewer (e.g. gtkwave its for free)
   http://gtkwave.sourceforge.net/

von bko (Guest)


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a typo: done -> dont

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