who is familiar with partial reconfiguration of fpgas?

I know that a Fraunhofer Institute is working on this. This guys makes 
the Franhofer sattelite "Heinrich Hertz" ready for take off in 2013 and 
as far as I know there is at least one FPGA based subsystem that can be 
partially reconfigured over the "air"...

Yes, maybe. The partial reconfiguration is a very academic topic, I 
think, there are only a few engineers in the world who deal with it.
I´m sorry but I also don´t have contact to such guys.

>As you are pioneer in the field of VHDL
Are you kidding?

Perhaps this helps:

http://www.doulos.com/content/training/xilinx_partial-reconfiguration.php

You may contact the chair for technical informatics (Lehrstuhl für 
Technische Informatik) at TU Dresden. The group of Prof. Spallek has 
done a lot of research on reconfiguration of FPGAs during runtime.

I have done something with these dynamic partial reconfiguration stuff 
during my diploma thesis 5 years ago. That is a very interesting topic. 
We used Virtex 1/2/4 and ISE 6.1 if I remember correct. That was before 
Xilinx was support partial reconfiguration officially. And it was very 
hard to get the tools to make, what we want. I don't know if it is 
simpler today.

I forgot: That research was done at Fraunhofer EAS in Dresden. And it 
was in conjunction with a project about high level synthesis.

> Dear Nerved
> thanks for the weblink.

***lol***

> The group of Prof. Spallek has
> done a lot of research on reconfiguration of FPGAs during runtime.

Me too, with the result, that P-FPGA-R (partial FPGA reconfig):

a) can save a lot of FPGA space, in dynamical systems, when math algos 
have to change

b) invokes a lot of development time and exponential amount of work for 
testing

c) is totally useless for most applications were big FPGAs are used, 
such as MIL / MED, because of validation issues.

An FPGA which dynamically changes it's behaviour during runtime has to 
be considered like software, and the larger the SW-Part in an FPGA, the 
more formal validation is required.

P-FPGA-R will always stay academic and experimental.

Search for 'partial reconfiguration' on this website:
http://www.fpl2012.org/program-all.shtml

With the names of the authors of this talks and posters you can go and 
search for the recent papers.

Duke

http://ces.itec.uka.de/~bauer/
http://primo.bibliothek.kit.edu/primo_library/libweb/action/display.do?tabs=detailsTab&ct=display&fn=search&doc=KITSRC31256872X&indx=1&recIds=KITSRC31256872X&recIdxs=0&elementId=0&renderMode=poppedOut&displayMode=full&frbrVersion=&dscnt=1&scp.scps=scope%3A%28%22KIT%22%29%2Cprimo_central_multiple_fe&frbg=&tab=kit_pc&dstmp=1347190287152&srt=rank&vl(3258244UI1)=all_items&mode=Basic&dum=true&tb=t&vl(1UIStartWith0)=contains&vl(3109087UI0)=any&vl(freeText0)=frank+birkle&vid=KIT

http://primo.bibliothek.kit.edu/primo_library/libweb/action/display.do?tabs=detailsTab&ct=display&fn=search&doc=KITSRC334794048&indx=1&recIds=KITSRC334794048&recIdxs=0&elementId=0&renderMode=poppedOut&displayMode=full&frbrVersion=&dscnt=1&scp.scps=scope%3A%28%22KIT%22%29%2Cprimo_central_multiple_fe&frbg=&tab=kit_pc&dstmp=1347190359988&srt=rank&vl(3258244UI1)=all_items&mode=Basic&dum=true&tb=t&vl(1UIStartWith0)=contains&vl(3109087UI0)=any&vl(freeText0)=jan+micha+borrmann&vid=KIT

http://primo.bibliothek.kit.edu/primo_library/libweb/action/display.do?frbrVersion=2&tabs=detailsTab&ct=display&fn=search&doc=KITSRC334799252&indx=1&recIds=KITSRC334799252&recIdxs=0&elementId=0&renderMode=poppedOut&displayMode=full&frbrVersion=2&dscnt=1&scp.scps=scope%3A%28%22KIT%22%29%2Cprimo_central_multiple_fe&frbg=&tab=kit_pc&dstmp=1347190374987&srt=rank&vl(3258244UI1)=all_items&mode=Basic&dum=true&tb=t&vl(1UIStartWith0)=contains&vl(3109087UI0)=any&vl(freeText0)=rispp&vid=KIT

Hallo

The University of Oslo (Department of Informatics) offers some 
publication with the Topic "Dynamic partial reconfiguration of FPGA"

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/

They also have developed a tool for Xilinx devices (Virtex 4,5,6 and 
Spartan 6).

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/goahead/


For the hobbyist how will play with that kind of technology, i have find 
a paper for "DPR" on a Spartan 6 (ICAP Interface and so on).

http://www.mn.uio.no/ifi/english/research/projects/cosrecos/publications/paper/raw11beckhoff.pdf

regards Patrick