Forum: FPGA, VHDL & Verilog Coding style suggestions for clocks and clock frequencies

von Martin S. (stmartin81)

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I'm trying to find some good coding guidelines regarding clock signals. 
I've used the approaches to append the frequency to the clock name (e.g. 
clk_2p5mhz). Another approach I took was to give the clocks specific 
names (e.g. clk_system).

But when I want to reuse components the clock names and the frequency of 
the clock could change.

I think the input clock can be named just "clk" or similar if the 
component doesn't need to know the frequency of the clock. Sometimes I 
need to count for a certain period of time and for that I need to know 
the frequency of the clock / clock period.

I though about using a generic which is of type time like this:
entity my_entity is
  generic (
    CLK_PERIOD_G : time
  port (
    CLK : std_logic;
end entity;

I'm interested to see what other coding styles you use.


von Lothar M. (lkmiller) (Moderator)

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You can also define a package and specify the clock frequency or the 
clock cycle time as a constant. But generics are more direct and 


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