I'm trying to find some good coding guidelines regarding clock signals.
I've used the approaches to append the frequency to the clock name (e.g.
clk_2p5mhz). Another approach I took was to give the clocks specific
names (e.g. clk_system).
But when I want to reuse components the clock names and the frequency of
the clock could change.
I think the input clock can be named just "clk" or similar if the
component doesn't need to know the frequency of the clock. Sometimes I
need to count for a certain period of time and for that I need to know
the frequency of the clock / clock period.
I though about using a generic which is of type time like this:
entity my_entity is
CLK_PERIOD_G : time
CLK : std_logic;
I'm interested to see what other coding styles you use.