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Forum: FPGA, VHDL & Verilog How can I print line numbers and file names in a VHDL testbench?


How can I print line numbers and file names in a VHDL testbench?
von Martin S. (stmartin81)

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Hello,

I'm working on a VHDL testbench where I use assert statements to check 
if the returned result is as expected. If a tests fails I would like to 
know in which line the test failed.

I'm using ISIM from Xilinx which doesn't print any line numbers for 
report statements.

Does anyone know if there exists a predefined function which returns the 
current line number?


Best regards
Martin

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