POR detection

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Ersin Oezalp wrote:

> Is there a way to detect power-on-reset situation in Spartan 6 with VHDL.

Hi Ersin,
first of all you might detect that your FPGA reside in Initialisation 
phase after Poweron...

There is no way to detect if your fpga will reside in Initialisation 
because of PowerOn or by activating "Config" or reconfigurate via JTAG.

Is that what you mean?

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