VHDL Hi everyone I have defined an type t11(array of recordtype) in a package A. I used this package 'A' in another package 'B' by typing "my use work.A.all" and proceeded using t11 here as below In package 'B' body 1.function blah1(c :t11) return t11 is 2.variable prod :t11; 3.begin 4.prod(0) := (0.0,0.0)-- as here i deal with real type 5.for i in 0 to amount-1 loop 6. prod(i) := blah2(prod (i), c(i) ) 7.end loop; 8.return prod; 9 end blah1; This is just part of my code in the package. and my main file is another one. When i try to simulate the main file i get this error "VARIABLE CANNOT BE UNCONSTRAINED" at this line 2 in package B. I am a bit new to this language and this site too :P. So please help me solve this error.Let me know if you need more info :)

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> This is just part of my code in the package.
Usually the posted part is the most unuseful one...
Why not attaching the whole code as *.vhd file(s)?
Enclose yourcode with [ vhdl ] and [ /vhdl ] (but without the blanks)
and you will see some little magic:
```

1 | function blah1(c :t11) return t11 is |

2 | variable prod :t11; |

3 | ```
begin
``` |

4 | prod(0) := (0.0,0.0)-- as here i deal with real type |

5 | |

6 | for i in 0 to amount-1 loop |

7 | prod(i) := blah2(prod (i), c(i) ) |

8 | end loop; |

9 | return prod; |

> type t11(array of recordtype) > variable prod :t11; This both will lead to the correct answer. Pls. post the original type definitions of all involved records/types... > I am a bit new to this language But you are using a lot of tricky tricks ... :-o > When i try to simulate the main file Hopefully you just want to simulate this, because you will (for sure!) not get it synthesized on real hardware...

haha. I have no intention of hiding the code :P. As I said I am new to this language, so the code is messy and was experimenting on it.I have not yet finished the coding fully. The problem lies in mat_ply package. I have enclosed both the packages here. Please excuse and correct me if they look wierd/wrong :P

There's the problem:

1 | type t11 is array (natural range<>) of comp; |

2 | ```
:
``` |

3 | ```
:
``` |

4 | variable prod1 : t11; |

```
>> "VARIABLE CANNOT BE UNCONSTRAINED"
Give the variable a size and try it this way:
variable prod1 : t11(0 to c'Length-1);
```

Yo!! absolutely. that solved the error.Thanks:) I have few more doubts with the code.You have previously mentioned that this cannot be synthesized.Is it because I am using real type or something else too? I would like to change it learning how to replace them with fixed point type(I have seen it on the net).How to use trignometry in vhdl? Like i want a tan inverse (or phase angle of a complex no.).

> You have previously mentioned that this cannot be synthesized. Yes. > Is it because I am using real type ... Yes. > I would like to change it learning how to replace them with fixed point > type(I have seen it on the net). The fixed_pkg is synthesizeable, because it bases on simple integer arithmetics, > How to use trignometry in vhdl? Uhmmm, oh, well... First, lets go some steps backwards... Youmustsee a FPGA as a heap of combinatorial logic (AND, OR, NAN, NOR, XOR...) and registers (Flipflops). Yor task ist to tell the synthesizer with VHDL code to assemble those two components (you don't have more on the FPGA) in a way they are doing the job you want. And now there's a very big gap in your way of thinking compared to a hardware designers way: you think in mathematics and calculations, the hardware guy in registers and rams and logic and (at maximum) a integer multiplier. But even a "simple" integer division will turn out as a complex demanding task when it has to be implemented on hardware... So the usual way is: implement those things which must be fast in hardware (basic calculations and simple maths), implement the "howto" in software and conntect the both of them with a vast statemachine called "processor".

Thanks for guiding me. I will habituate to your way of approach Now I am supposed to find the tan inverse. So I have use simple maths which comes to mind as taylor's series. I am just afraid that cannot be accurate enough(I am not sure until I simulate and compare the results) because i couldn't write the whole series of it. Please clarify whether going for taylor's series is a good option or not in the hardware sense

> I am just afraid that cannot be accurate enough > (I am not sure until I simulate and compare the results) How accurate is float? With a "usual" IEEE float you have only about 7.5 decimal digits accuracy! So you cannot distiguish between a 12345,677 and a 12345,673... :-o A integer has about 9.5 decimal digits accuracy, that is nearly 8 bits more (of course itmustbe so, because the float mantissa-bits are used for more accuracy). But that hasnothingto do with VHDL, its pure maths and the basics of binary calculation. A hint: the most accurate calculators without limitation in length are doing the calcs like you do it. Treat the numbers as single digits and weigh them according to thier position inside the number (...., tenthousands, thousands, hundreds, tens, ones, tenths, hundreths, ....). But you don't want to do that in hardware...

Thanks for your advices :). You were very helpful and informative.Let the thread be closed if it has to .I will start a new thread if i come across anymore problems :). Glad to be on this forum