Currently 'm working on hardware implementation of neural cryptography and i have written the verilog code for it.the code has been complied using Xilinx ISE 9.0.but now it has to be fed onto the FPGA kit ie ELBERT SPARTAN 3E,how is it done? Also, will the performance of the program differ once loaded onto the kit when compared to the simulator?
> now it has to be fed onto the FPGA kit ie ELBERT SPARTAN 3E, > how is it done? Got to the xilinx homepage and search for "configuration" Or try google: http://www.google.com/search?q=xilinx+configuration And for the i.E. EELBERT board there is a users guide, explaining a lot of things: http://numato.com/elbert-spartan-3a-fpga-development-board-user-guide and also the configuration: http://numato.com/elbert-spartan-3a-fpga-development-board-user-guide#ProgrammingElbert > Also, will the performance of the program differ once loaded > onto the kit when compared to the simulator? Of course the performance will be MUCH better. Because simulating a HDL code with a clock of 100MHz (=10ns) for 100 million cycles (=1s) can take up to half an hour (or much longer). And because 1s is much less than 30min the real system will be much faster. BUT first: your design must be able to cope up with 100MHz. And to get this, you have to use TIMING CONSTRAINTS. To keep things short: a functional simulation does say nothing at all about the maximum operating frequency!
Lothar, I think he asked different No, the performance of the program wil not differ compared to the simulator if the synthesis tool routs all and meets timing , it will work how is it done? xilinx impact