Serial_Converter

OP (Company: iqi labs) #2732243
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Hi can any 1 plz help me,
 My task is to convert the parallel data into serial of 32 bit i have 
written the code it gt implemented but in test bench iam founding some 
errors please verify it and suggest me please.
       When the load is high the data should get stored or loaded into 
the register and when it is low it should get shifted. This is the topic 
which i have done.
  please help me out of this, thanks in advance.
OP (Company: iqi labs) #2732408
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if i delete that line getting 3 errors like
# ** Error: 
D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb 
.vhd(91):  No feasible entries for infix operator "+".

# ** Error: 
D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb 
.vhd(91):  Type error resolving infix expression "+" as type 
ieee.std_logic_1164.std_logic_vector.

# ** Error: 
D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb 
.vhd(96):  near "=": syntax error

then what to do
Moderator (Company: Titel) #2732463
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> No feasible entries for infix operator "+".
Take any vhdl book and read the first few pages....

However: this simple message means that the simulator does not know, how 
to add a integer to a std_logic_vector. Tell it to him by adding the 
old fashioned and obsolete IEEE.std_logic_unsigned.all. In that package 
the desired unsigend addition is defined...

What about looking, how others are doing such things?
Google is a very recommended place for such error messages:
http://www.google.com/search?q=No+feasible+entries+for+infix+operator


BTW:
1
USE IEEE.std_logic_arith.all;
2

3
USE ieee.numeric_std.ALL;

Use these old obsolete Libs:
 IEEE.std_logic_arith.all;
 IEEE.std_logic_unsigned.all;

Or this new and fresh one:
 ieee.numeric_std.ALL;

But NEVER EVER all of them TOGETHER!

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