Hi can any 1 plz help me, My task is to convert the parallel data into serial of 32 bit i have written the code it gt implemented but in test bench iam founding some errors please verify it and suggest me please. When the load is high the data should get stored or loaded into the register and when it is low it should get shifted. This is the topic which i have done. please help me out of this, thanks in advance.
> i am founding some errors
Some secret errors?
If the errrors are not secret, then pls. tell WHICH ones!
I just modified little bit and again a error like, # ** Error: D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb .vhd(31): near "USE": expecting '[' or '(' or '.' or ''' so where and how to modify this and iam attachin the file which is modified too.
The error message gives you - line number (31) - error description What do you expect more?
ya but even when modifying its not clearing that is what i need how to rectify it
Hi, I think there is a ';' missing at the end of this line:
1 | USE ieee.std_logic_1164.std_logic_vector |
Cheers
> I think there is a ';' missing at the end of this line:
And the most simple solution will be to delete that line, because in the
previous line .ALL is included...
1 | USE ieee.std_logic_1164.ALL; |
2 | USE ieee.std_logic_1164.std_logic_vector |
if i delete that line getting 3 errors like # ** Error: D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb .vhd(91): No feasible entries for infix operator "+". # ** Error: D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb .vhd(91): Type error resolving infix expression "+" as type ieee.std_logic_1164.std_logic_vector. # ** Error: D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb .vhd(96): near "=": syntax error then what to do
> No feasible entries for infix operator "+". Take any vhdl book and read the first few pages.... However: this simple message means that the simulator does not know, how to add a integer to a std_logic_vector. Tell it to him by adding the old fashioned and obsolete IEEE.std_logic_unsigned.all. In that package the desired unsigend addition is defined... What about looking, how others are doing such things? Google is a very recommended place for such error messages: http://www.google.com/search?q=No+feasible+entries+for+infix+operator BTW:
1 | USE IEEE.std_logic_arith.all; |
2 | |
3 | USE ieee.numeric_std.ALL; |
Use these old obsolete Libs: IEEE.std_logic_arith.all; IEEE.std_logic_unsigned.all; Or this new and fresh one: ieee.numeric_std.ALL; But NEVER EVER all of them TOGETHER!
that is cleared but 1 error is coming but which is a syntax error even i did many changes its not resolving # ** Error: D:/Anjali/Data_Simulator/27th_June/Serial_Convertertb/Serial_Convertertb .vhd(96): near "=": syntax error
i resolved it , thank u soo much for your posts i resolved the errors now it got simulated thanks alot
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.