Hi! I've got a small problem with my current code and would appreciate any help. I tried to find someone with a similar problem, but my google skills aren't good enough. This is basically the problem that I'm facing: generic_a is a generic natural signal, that have to be positive. slv_a is defined as a STD_LOGIC_VECTOR(15 DOWNTO 0).
IF (generic_a <= 15) then slv_a(generic_a) <= '1'; END IF;
The problem with this code is when generic_a is bigger then 15. Then I get an error because the statement above points at a position that is out of range, even though the illegal statement never will be executed. How can I solve this without changing the size of slv_a and without limeting the values that generic_a can take? Thankful for any help, VHDL_Turtle
> Then I get an error Where do you get this error? In simulation? Or in real life? What kind of error do you get?
Haha! "In real life" :-P I get the error when I try to simulate the code in ModelSim and I set generic_a to a big number, say 25. The error that I get is something like "index out of bounds" (don't have acces to my code right now so I can't give an exakt error code) The reason why the code is generating a error is because the middle line becomes:
slv_a(25) <= '1'; -- Generates a error even though it is never executed
Which gives an error because slv_a is only defined as 16 bits wide. How do I remove this problem? Because I still want to be able to simulate my code when generic_a is big. Sincerely, VHDL_Turtle
Try it with a trick and do a modulo operation on generic_a: slv_a(generic_a mod 15) Or because generic_a is a generic and therefore locally constant: try it with a conditional generate instead of a simple if... But for better diagnosis there should be more code/information (type definitions, used packages, ...).
Oh, that little mod-trick is brilliant! That will solve my problem! Some sort of generate would probably be the best solution to my problem. But that mod-trick is alot easier then it is to use the concurrent generate-statement inside a sequencial process statement. Thank you for your help Lothar! Sincerely, VHDL_Turtle