Hi! I've got a small problem with my current code and would appreciate any help. I tried to find someone with a similar problem, but my google skills aren't good enough. This is basically the problem that I'm facing: generic_a is a generic natural signal, that have to be positive. slv_a is defined as a STD_LOGIC_VECTOR(15 DOWNTO 0).
IF (generic_a <= 15) then
slv_a(generic_a) <= '1';
The problem with this code is when generic_a is bigger then 15. Then I get an error because the statement above points at a position that is out of range, even though the illegal statement never will be executed. How can I solve this without changing the size of slv_a and without limeting the values that generic_a can take? Thankful for any help, VHDL_Turtle