VHDL simulation waveform problems

Hello everyone, this is my first post here.
Thanks in advance for reading my problem.

Well, I have to create a vhdl code for a 2bit counter, which receives 
8bits (where only 3 of them are '1'), and adds 1 to the counter for 
every '1' inside those 8bits

I created another signal, "conta", and assigned the variable count to it 
inside the process, and so assigned "conta" to the output "contador" 
outside the process

Now the "contador" isn't adding when A(i) <= '1'.
I guess there may be a problem the way I attached the signals and 
variable inside/outside the process.

Maybe the code isn't proper for what I want, cause I'm a beginner trying 
to learn by myself.

If my question is too basic, I would appreciate a link where I could 
understand it thoroughly. I got to send a project next friday.
Right now the code is like:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contador_acertos is

port (clock, reset, enable : in std_logic;
      acertos : in std_logic_vector(7 downto 0);
      contador : out std_logic_vector(1 downto 0)

      );

end contador_acertos;

architecture behavior_contagem of contador_acertos is
signal A : std_logic_vector(7 downto 0);
signal conta : std_logic_vector(1 downto 0);
begin
A <= acertos;
process (clock, acertos, enable, reset)
variable count : std_logic_vector(1 downto 0);
begin
  if (reset = '1') then
  count := "00";
    elsif (clock'event and clock = '1') then
    if (enable <= '1') then


      count := "00";

      oito : for i in 7 downto 0 loop
      if (A(i) <= '1') then
      count := count + 1;
      end if;
      end loop oito;

end if;
end if;
conta <= count;
end process;
contador <= conta;
end behavior_contagem;