Forum: FPGA, VHDL & Verilog Need help with VHDL code for metal detector

von Roel s. (roelst)

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I am working on a metal detector at the moment but cant figure out how 
to implement it my VHDL code.
ENTITY sensor IS
     port ( metaldetector : in std_logic;
            metal : out std_logic;
END ENTITY sensor;
As long as there isnt any metal close to the sensor 'metaldetector' gets 
pulses on a 6.1kHz frequency. So as long as the 'metaldetector' keeps 
getting pulses the out port 'metal' should be '0'.

When there is a pulse missing (or multiple pulses) 'metal' should become 
'1' until the next pulse.

It shouldnt be that hard to make a code that can do that, but i just 
cant figure it out. Any help would realy be great!

von P. K. (pek)

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You need a reference clock of some kind.

Then, implement a watchdog counter. If the counter is bigger than the 
required trigger value, stop counting and set metal = '1'. Restart the 
counter and set metal = '0' with each pulse you get.

As the reference clock is asynchronous (most probably) don't forget 
proper synchronisation.

von Roel s. (roelst)

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tell me about this watchdog counter (could you give me an example?). 
Google isnt helping me out here :/


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