hello, when i am generating division core ..this particular warning is oming.. WARNING:sim:471 - The chosen IP does not support a VHDL behavioral model, generating a VHDL structural model instead. Initialising IP model... WARNING:sim:472 - The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead. because of this warning, divion core is not producing any remainder and fractional.. please help me.. regards,
> because of this warning, divion core is not producing any remainder > and fractional.. Why do you think so? A structural model usually will be "enough" for simulation...
Reply
Please log in before posting.