Interfacing a Spartan 6' MCB to a DDR3 physically

The two Pins mentioned are AFAIK required by the physical controller. 
Xilinx has some explanation in their docs.

Ok, I got some information in the meanwhile, so these two pins are a 
minor issue now.

What bothers be more are design aspects like termination. Specs from 
Micron do contradict some recommendations I found in the xilinx' docs 
and also the PCB doc shows different routing and termination than 
expected.

For example, I do not find the data and adresss signals beeing 
terminated.

Moreover the coregen seems to be buggy and does not lead to a 
synthesizeable design, which I could test in order to find out about 
certain issues myself.

Modern DDR memory chips use on-die termination, which is controlled by 
the ODT line.

In order to get the MIG design to run, you definitely need to modify the 
top-level HDL of the generated design (usually located in 
ipcore_dir/core_name/user_design), especially regarding the clock 
frequency parameters to fit to your hardware.

Hope this helps.

> Modern DDR memory chips use on-die termination, which is
> controlled by the ODT line.

Hm, I am following the discussion, since I also intend to do a design 
with DDR3 (FPGA not yet decided).

I have read the micron's manual and also find termination resistor 
recommendations. From your words ODT is the best practise so to speak?

ok, thanks for your help so far.

Regarding modifying the design: The wrapper seams to instantiate it's 
own PLL. What do I have to select for the clock?

Is it necessary to feed that directly from an IO pin? Will it require 
it's own osc?

Or in other words - Can I use the generated PLL also for my design?

Aother Question:

From the micron's manual, there is a note like that:

"regardless of bus type, all DDR signals must be referenced to VSS or 
VDD plane."

Does that mean, they have to be "terminated" or routed "next to" / "on 
top of" a vss plane?

nobody listening?

Hallo Thomas,

>"regardless of bus type, all DDR signals must be referenced to VSS or VDD plane."
>Does that mean, they have to be "terminated" or routed "next to" / "on top of" a 
vss plane?

This means, that all signal should be referenced to a planed layer.

Vanilla

Hallo Schwabenpaule,

> Regarding modifying the design: The wrapper seams to instantiate it's own PLL. 
What do I have to select for the clock?

> Is it necessary to feed that directly from an IO pin? Will it require it's own 
osc?

> Or in other words - Can I use the generated PLL also for my design

The CoreGenerater will create the PLL instance for you. You will get a 
HDL description.
You are free to modify this, and probably add and modify the PLL to 
provide additional frequencies.

About feeding directly from IO-Pin.
This is (highly) recomended from Xilinx to avoid additional jitter. 
There are also recomendations to use the dedicated PLL ancient to the 
used MPMC.
you might use one PLL for MPMCs on the opposite MPMC side, but this also 
adds jitter to the clock and migt be crittical if running the MPMCs at 
the maximum supported speed.

best regards

Vanilla

what you mean with "referenced"?

does this mean "terminated to this plane"?