Forum: FPGA, VHDL & Verilog Combinational logic based ALU

von John (Guest)

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Hi, I'm running into a problem that probably has a (really) easy fix but 
I can't seem to find it:
module MemAndALU(input wire [2:0]f, input wire [31:0]A,B, output [31:0]Y, output Z,N);

wire Cout;
wire [31:0]sum;

if(f==3'b000) begin
  ripple_carry_adder RCA(Cout, sum, A, B, 1'b0);
  assign Y=sum;

    assign Z=1;
    assign Z=0;
    assign N=1;
    assign N=0;

One of the errors I'm getting is
Error (10149): Verilog HDL Declaration error at MemAndALU.v(7): 
identifier "sum" is already declared in the present scope


Error (10759): Verilog HDL error at MemAndALU.v(7): object A declared in 
a list of port declarations cannot be redeclared within the module body

I can't use registers for this assignment (which is frustrating) The 
header for ripple_carry_adder is here
module ripple_carry_adder
  output Cout,
  output [31:0]Sum,
  input [31:0]A,
  input [31:0]B,
  input Cin
and I know that it works

von Duke Scarring (Guest)

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Try to remove the following line:
wire Cout;



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