Is it possible to get the system date/time in my VHDL simulation (it is 
a test bench written in VHDL). I want to include the date/time in the 
name of the log file(that I create and write to using texio) so they 
don't over right each other. I am using ModelSim 6.6 to run it if that 
matters.

Yes. You can use TCL to build a "time"-string and give it to your 
simulation as generic, like in this example:

set logfilename "logfile_"
append logfilename [clock format [clock seconds] -format %H_%M]
vsim -Glogfilename=$logfilename work.entity

Duke