Is it possible to get the system date/time in my VHDL simulation (it is a test bench written in VHDL). I want to include the date/time in the name of the log file(that I create and write to using texio) so they don't over right each other. I am using ModelSim 6.6 to run it if that matters.
:
Yes. You can use TCL to build a "time"-string and give it to your simulation as generic, like in this example:
1 | set logfilename "logfile_" |
2 | append logfilename [clock format [clock seconds] -format %H_%M] |
3 | vsim -Glogfilename=$logfilename work.entity |
Duke
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