I'm designing a single-cycle CPU in Verilog, compiling using Chronologic
VCS v. 2006 on a Sun Linux server. Below is a trimmed up version of the
code that's giving me trouble, and the exact verbatim code below is
still giving me the error:
Parsing design file 'test.v'
Error-[SE] Syntax error
"test.v", 5: token is '['
reg_array[0] = 134;
^
1 error
CPU time: 0 seconds to compile
1 | module regfile;
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2 |
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3 | reg [31:0] reg_array[0:31]; //array of 32-bit registers
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4 |
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5 | reg_array[0] = 134;
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6 | reg_array[2] = 854;
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7 | reg_array[6] = 223;
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8 | reg_array[7] = 4878;
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9 | reg_array[8] = 9855;
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10 | reg_array[10] = 2;
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11 | reg_array[20] = 0;
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12 | reg_array[21] = 1;
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13 | reg_array[31] = 5555;
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14 |
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15 | endmodule
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I assume it is a painfully simple solution but I am too tired and stupid
to find it right now. Fresh eyes appreciated. Thanks all!