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Forum: FPGA, VHDL & Verilog Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA


Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von anjali k. (Company: iqi labs) (anjali)

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HI,
 can any 1 say me, IS MIG core generator usage for this problem is 
correct?
 By using MIG can we generate a code for interfacing Controller to an 
FPGA?
 THANKS IN ADVANCE.

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von Erich Milke (Guest)

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What else would one suggest to instatiate a core??? Megawizzard?

Maybe you can try Microsoft's Virtual Sheep Message Translator, but it 
would not work either for this "problem", I'm afraid.

Sorry for kidding but what kind of question is that?

You should try to get familiar with FPGAs, Virtex and especially Xilinx' 
Document Manager to dig out the appropriate information.

I wonder how you can create software at all there overseas, not even 
beeing able to read the documents coming along with your software.

gez. Erich Milke, ehemaliger "DDR-Controller".

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von Harri Deutsch (Guest)

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>ehemaliger "DDR-Controller"

***lol***

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von anjali k. (Company: iqi labs) (anjali)

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Hi,
i implemented the code for interfacing DDR3 SDRAM to an FPGA it got 
synthesized but not getting translated showing 2 errors of following:

ERROR : :NgdBuild:604 - logical block 'INST_Buttons_VHDL' with type 
'Buttons_VHDL'could not be resolved. A pin name misspelling can cause 
this, a missing edif or ngc file, case mismatch between the block name 
and the edif or ngc file name, or the misspelling of a type name. Symbol 
'Buttons_VHDL' is not supported in target 'virtex6'.

ERROR:NgdBuild:604 - logical block 'INST_DDR3_RAM_CORE' with type
   'DDR3_Ram_Core' could not be resolved. A pin name misspelling can 
cause this,a missing edif or ngc file, case mismatch between the block 
name and the edif or ngc file name, or the misspelling of a type name. 
Symbol 'DDR3_Ram_Core' is not supported in target 'virtex6'.

 Iam attatching my code also once check it out

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von Nicola Sarkozy (Guest)

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Hello, you are lucky!

Since now, I have much time and can deal with all the problems in the 
world.

Please send me all your code and I can do it right for you.

The first 5 people who send me their code will b satisfied.

The others might have a look into the xilinx forum. I heard, that the is 
a similar thread open. Bob Elind already answered.

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von anjali k. (Company: iqi labs) (anjali)

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HI, i have generated the code for ddr3 interfacing with virtex6 fpga but 
iam unable to understand is that right or wrong.
      Iam attatching the file plz check it out and say me.
   Thank you in Advance.

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Re: Interfacing DDR3 SDRAM memory controller to an virtex 6 FPGA
von Angela Merkel (Guest)

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Hi

This is why I always tell our german industry to move their know-how to 
india...

Indeed... don't get me wrong,
but from a VHDL point of view your are on a "hello-world" level (with 
compile errors) and are trying to write a 3D-Egoshooter.

Cheers.

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