Dear All,
i wanna to understand this vhdl code please,

signal x,y : bit_vector(0 to 7);
A_loop: for i in x'range loop
b_loop: for j in y'range loop
next a_loop when i<j;
end loop b_loop;
end loop a_loop;

thanks,

> i wanna to understand this vhdl code please
> next a_loop when i<j;
You cannot understand anything, because this code makes no sense!
Its incomplete, something is missing...