EmbDev.net

Forum: FPGA, VHDL & Verilog Ripple Carry Adder and quartus


von John (Guest)


Rate this post
0 useful
not useful
Hi, I'm having trouble getting two files to work in quartus.

Here is full_adder.v
1
module full_adder(S, Cout, A, B, Cin);
2
  output S;
3
  output Cout;
4
  input A;
5
  input B;
6
  input Cin;
7
  wire nor1_out, and1_out, and2_out;
8
  nor nor1(nor1_out,A,B);
9
  nor nor2(S, nor1_out, Cin);
10
  and and1(and1_out, Cin, nor1_out);
11
  and and2(and2_out, A, B);
12
  or or1(Cout, and1_out, and2_out);
13
endmodule

And here is ripple_carry_adder.v
1
module ripple_carry_adder
2
(
3
  output Cout, 
4
  output [7:0]Sum, 
5
  output overflow_flag, 
6
  input [7:0]A, 
7
  input [7:0]B, 
8
  input Cin
9
);
10
reg mytemp, mytemp2;
11
12
full_adder A1(Sum[0], mytemp, A[0], B[0], Cin);
13
full_adder A2(Sum[1], mytemp2, A[1], B[1], mytemp);
14
full_adder A3(Sum[2], mytemp, A[2], B[2], mytemp2);
15
full_adder A4(Sum[3], mytemp2, A[3], B[3], mytemp);
16
full_adder A5(Sum[4], mytemp, A[4], B[4], mytemp2);
17
full_adder A6(Sum[5], mytemp2, A[5], B[5], mytemp);
18
full_adder A7(Sum[6], mytemp, A[6], B[6], mytemp2);
19
full_adder A8(Sum[7], Cout, A[7], B[7], mytemp);
20
21
//if(Cout==1) overflow_flag=1;
22
//else overflow_flag=0;
23
endmodule

I'm getting and error that says "Verilog HDL Port Connection error at 
ripple_carry_adder.v(12): output or inout port "Cout" must be connected 
to a structural or net expression", and I've looked over my code but 
can't figure it out.  I have included both verilog files in my project.

von bko (Guest)


Rate this post
0 useful
not useful
reg for "mytemp*" is wrong, it should be wire:
> your code
> reg mytemp, mytemp2;  <<<=== does not work

should be
1
wire mytemp, mytemp2;

von John (Guest)


Rate this post
0 useful
not useful
Thank you that worked! For anyone else that has this problem in the 
future, it also wouldn't let me stagger mytemp and mytemp2 like that, I 
had to make an array [7:0]mytemp

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.