Forum: FPGA, VHDL & Verilog Ripple Carry Adder and quartus

von John (Guest)

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Hi, I'm having trouble getting two files to work in quartus.

Here is full_adder.v
module full_adder(S, Cout, A, B, Cin);
  output S;
  output Cout;
  input A;
  input B;
  input Cin;
  wire nor1_out, and1_out, and2_out;
  nor nor1(nor1_out,A,B);
  nor nor2(S, nor1_out, Cin);
  and and1(and1_out, Cin, nor1_out);
  and and2(and2_out, A, B);
  or or1(Cout, and1_out, and2_out);

And here is ripple_carry_adder.v
module ripple_carry_adder
  output Cout, 
  output [7:0]Sum, 
  output overflow_flag, 
  input [7:0]A, 
  input [7:0]B, 
  input Cin
reg mytemp, mytemp2;

full_adder A1(Sum[0], mytemp, A[0], B[0], Cin);
full_adder A2(Sum[1], mytemp2, A[1], B[1], mytemp);
full_adder A3(Sum[2], mytemp, A[2], B[2], mytemp2);
full_adder A4(Sum[3], mytemp2, A[3], B[3], mytemp);
full_adder A5(Sum[4], mytemp, A[4], B[4], mytemp2);
full_adder A6(Sum[5], mytemp2, A[5], B[5], mytemp);
full_adder A7(Sum[6], mytemp, A[6], B[6], mytemp2);
full_adder A8(Sum[7], Cout, A[7], B[7], mytemp);

//if(Cout==1) overflow_flag=1;
//else overflow_flag=0;

I'm getting and error that says "Verilog HDL Port Connection error at 
ripple_carry_adder.v(12): output or inout port "Cout" must be connected 
to a structural or net expression", and I've looked over my code but 
can't figure it out.  I have included both verilog files in my project.

von bko (Guest)

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reg for "mytemp*" is wrong, it should be wire:
> your code
> reg mytemp, mytemp2;  <<<=== does not work

should be
wire mytemp, mytemp2;

von John (Guest)

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Thank you that worked! For anyone else that has this problem in the 
future, it also wouldn't let me stagger mytemp and mytemp2 like that, I 
had to make an array [7:0]mytemp


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