Hi, I'm having trouble getting two files to work in quartus.
Here is full_adder.v

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modulefull_adder(S,Cout,A,B,Cin);

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outputS;

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outputCout;

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inputA;

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inputB;

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inputCin;

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wirenor1_out,and1_out,and2_out;

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nornor1(nor1_out,A,B);

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nornor2(S,nor1_out,Cin);

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andand1(and1_out,Cin,nor1_out);

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andand2(and2_out,A,B);

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oror1(Cout,and1_out,and2_out);

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endmodule

And here is ripple_carry_adder.v

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moduleripple_carry_adder

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(

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outputCout,

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output[7:0]Sum,

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outputoverflow_flag,

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input[7:0]A,

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input[7:0]B,

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inputCin

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);

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regmytemp,mytemp2;

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full_adderA1(Sum[0],mytemp,A[0],B[0],Cin);

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full_adderA2(Sum[1],mytemp2,A[1],B[1],mytemp);

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full_adderA3(Sum[2],mytemp,A[2],B[2],mytemp2);

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full_adderA4(Sum[3],mytemp2,A[3],B[3],mytemp);

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full_adderA5(Sum[4],mytemp,A[4],B[4],mytemp2);

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full_adderA6(Sum[5],mytemp2,A[5],B[5],mytemp);

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full_adderA7(Sum[6],mytemp,A[6],B[6],mytemp2);

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full_adderA8(Sum[7],Cout,A[7],B[7],mytemp);

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//if(Cout==1)overflow_flag=1;

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//elseoverflow_flag=0;

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endmodule

I'm getting and error that says "Verilog HDL Port Connection error at
ripple_carry_adder.v(12): output or inout port "Cout" must be connected
to a structural or net expression", and I've looked over my code but
can't figure it out. I have included both verilog files in my project.

Thank you that worked! For anyone else that has this problem in the
future, it also wouldn't let me stagger mytemp and mytemp2 like that, I
had to make an array [7:0]mytemp