Hi.. i need help to call 1 VHDL code to other VHDL code.. i have 2 VHDL code (Rotary_switch and buzzer).. that program work well and i can run it at FPGA.. and now i need to call buzzer.vhdl at rotary.vhdl. but i dont know how to do that.. this is my vhdl code for rotary_switch
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | |
6 | -- Uncomment the following library declaration if using
|
7 | -- arithmetic functions with Signed or Unsigned values
|
8 | --use IEEE.NUMERIC_STD.ALL;
|
9 | |
10 | -- Uncomment the following library declaration if instantiating
|
11 | -- any Xilinx primitives in this code.
|
12 | --library UNISIM;
|
13 | --use UNISIM.VComponents.all;
|
14 | |
15 | entity main is |
16 | port( clk: in STD_LOGIC; |
17 | rot_a: in STD_LOGIC; |
18 | rot_b : in STD_LOGIC; |
19 | rot_center : in STD_LOGIC; |
20 | J4 : out STD_LOGIC; |
21 | led : out STD_LOGIC_VECTOR (7 downto 0):="00000000"); |
22 | end main; |
23 | |
24 | architecture Behavioral of main is |
25 | |
26 | signal rotary_a_in: std_logic; |
27 | signal rotary_b_in: std_logic; |
28 | signal rotary_q1: std_logic; |
29 | signal rotary_q2: std_logic; |
30 | signal rotary_in: std_logic_vector(1 downto 0); |
31 | signal rotary_event: std_logic; |
32 | signal rotary_left:std_logic; |
33 | signal delay_rotary_q1:std_logic; |
34 | signal center_flag:std_logic; |
35 | |
36 | begin
|
37 | |
38 | rotary_a_in <= rot_a; |
39 | rotary_b_in <= rot_b; |
40 | |
41 | rotary_filter: process(clk) |
42 | begin
|
43 | if clk'event and clk='1' then |
44 | rotary_in <= rotary_b_in & rotary_a_in; |
45 | |
46 | case rotary_in is |
47 | when "00" => rotary_q1 <= '0'; |
48 | rotary_q2 <= rotary_q2; |
49 | when "01" => rotary_q1 <= rotary_q1; |
50 | rotary_q2 <= '0'; |
51 | when "10" => rotary_q1 <= rotary_q1; |
52 | rotary_q2 <= '1'; |
53 | when "11" => rotary_q1 <= '1'; |
54 | rotary_q2 <= rotary_q2; |
55 | when others => rotary_q1 <= rotary_q1; |
56 | rotary_q2 <= rotary_q2; |
57 | end case; |
58 | end if; |
59 | end process rotary_filter; |
60 | |
61 | direction: process(clk) |
62 | begin
|
63 | if clk'event and clk='1' then |
64 | |
65 | delay_rotary_q1 <= rotary_q1; |
66 | if rotary_q1='1' and delay_rotary_q1='0' then |
67 | rotary_event <= '1'; |
68 | rotary_left <= rotary_q2; |
69 | else
|
70 | rotary_event <= '0'; |
71 | rotary_left <= rotary_left; |
72 | end if; |
73 | end if; |
74 | end process direction; |
75 | |
76 | led_switch: process(clk,rotary_event,rotary_left) |
77 | |
78 | variable i : integer:=8; |
79 | variable index : integer; |
80 | begin
|
81 | if clk'event and clk='1' then |
82 | if rotary_event='1' and rotary_left='0' then --left |
83 | index :=i mod 8; |
84 | led(index)<='1'; |
85 | if index=3 then |
86 | J4<='1'; |
87 | --I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON..
|
88 | end if; |
89 | i:=i+1; |
90 | if i=8 then |
91 | i:=7; |
92 | end if; |
93 | end if; |
94 | if rotary_event='1' and rotary_left='1' then --right |
95 | if i=8 then |
96 | i:=7; |
97 | end if; |
98 | index :=i mod 8; |
99 | led(index)<='0'; |
100 | i:=i-1; |
101 | if index=3 then |
102 | J4<='0'; |
103 | end if; |
104 | if i=0 then |
105 | i:=1; |
106 | led(0)<='1'; |
107 | end if; |
108 | end if; |
109 | end if; |
110 | end process led_switch; |
111 | |
112 | process(rot_center) |
113 | begin
|
114 | if (rot_center='1') then |
115 | center_flag<='1'; |
116 | elsif (rot_center='0') then |
117 | center_flag<='0'; |
118 | end if; |
119 | end process; |
120 | |
121 | end Behavioral; |
this is my vhdl code for buzzer
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.STD_LOGIC_ARITH.ALL; |
4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
5 | |
6 | ENTITY buzzer IS |
7 | PORT ( |
8 | clk : IN std_logic; |
9 | rst : IN std_logic; |
10 | out_bit : OUT std_logic); |
11 | END buzzer; |
12 | |
13 | ARCHITECTURE arch OF buzzer IS |
14 | |
15 | |
16 | SIGNAL clk_div1 : std_logic_vector(3 DOWNTO 0); |
17 | SIGNAL clk_div2 : std_logic_vector(12 DOWNTO 0); |
18 | SIGNAL cnt : std_logic_vector(21 DOWNTO 0); |
19 | SIGNAL state : std_logic_vector(2 DOWNTO 0); |
20 | CONSTANT duo : std_logic_vector(12 DOWNTO 0) :="0111011101110"; |
21 | CONSTANT lai : std_logic_vector(12 DOWNTO 0) := "0110101001101"; |
22 | CONSTANT mi : std_logic_vector(12 DOWNTO 0) := "0101111011010"; |
23 | CONSTANT fa : std_logic_vector(12 DOWNTO 0) := "0101100110001"; |
24 | CONSTANT suo : std_logic_vector(12 DOWNTO 0) := "0100111110111"; |
25 | CONSTANT la : std_logic_vector(12 DOWNTO 0) := "0100011100001"; |
26 | CONSTANT xi : std_logic_vector(12 DOWNTO 0) := "0011111101000"; |
27 | CONSTANT duo1 : std_logic_vector(12 DOWNTO 0) := "0011101110111"; |
28 | SIGNAL out_bit_tmp :std_logic; |
29 | |
30 | BEGIN
|
31 | out_bit<=out_bit_tmp; |
32 | PROCESS(clk,rst) |
33 | BEGIN
|
34 | IF (NOT rst = '1') THEN |
35 | clk_div1 <= "0000"; |
36 | ELSif(clk'event and clk='1')then |
37 | IF (clk_div1 /= "1100") THEN |
38 | clk_div1 <= clk_div1 + "0001"; |
39 | ELSE
|
40 | clk_div1 <= "0000"; |
41 | END IF; |
42 | END IF; |
43 | END PROCESS; |
44 | |
45 | PROCESS(clk,rst) |
46 | BEGIN
|
47 | |
48 | IF (NOT rst = '1') THEN |
49 | clk_div2 <= "0000000000000"; |
50 | state <= "000"; |
51 | cnt <= "0000000000000000000000"; |
52 | out_bit_tmp <= '0'; |
53 | ELSif(clk'event and clk='1')then |
54 | IF (clk_div1 = "1001") THEN |
55 | CASE state IS |
56 | WHEN "000" => |
57 | cnt <= cnt + "0000000000000000000001"; |
58 | IF (cnt = "1111111111111111111111") THEN |
59 | state <= "001"; |
60 | END IF; |
61 | IF (clk_div2 /= duo) THEN |
62 | clk_div2 <= clk_div2 + "0000000000001"; |
63 | ELSE
|
64 | clk_div2 <= "0000000000000"; |
65 | out_bit_tmp <= NOT out_bit_tmp; |
66 | END IF; |
67 | WHEN "001" => |
68 | cnt <= cnt + "0000000000000000000001"; |
69 | IF (cnt = "1111111111111111111111") THEN |
70 | state <= "010"; |
71 | END IF; |
72 | IF (clk_div2 /=lai) THEN |
73 | clk_div2 <= clk_div2 + "0000000000001"; |
74 | ELSE
|
75 | clk_div2 <= "0000000000000"; |
76 | out_bit_tmp <= NOT out_bit_tmp; |
77 | END IF; |
78 | WHEN "010" => |
79 | cnt <= cnt + "0000000000000000000001"; |
80 | IF (cnt = "1111111111111111111111") THEN |
81 | state <= "011"; |
82 | END IF; |
83 | IF (clk_div2 /=mi) THEN |
84 | clk_div2 <= clk_div2 + "0000000000001"; |
85 | ELSE
|
86 | clk_div2 <= "0000000000000"; |
87 | out_bit_tmp <= NOT out_bit_tmp; |
88 | END IF; |
89 | WHEN "011" => |
90 | cnt <= cnt + "0000000000000000000001"; |
91 | IF (cnt = "1111111111111111111111") THEN |
92 | state <= "100"; |
93 | END IF; |
94 | IF (clk_div2 /=fa) THEN |
95 | clk_div2 <= clk_div2 + "0000000000001"; |
96 | ELSE
|
97 | clk_div2 <= "0000000000000"; |
98 | out_bit_tmp <= NOT out_bit_tmp; |
99 | END IF; |
100 | WHEN "100" => |
101 | cnt <= cnt + "0000000000000000000001"; |
102 | IF (cnt = "1111111111111111111111") THEN |
103 | state <= "101"; |
104 | END IF; |
105 | IF (clk_div2 /=suo) THEN |
106 | clk_div2 <= clk_div2 + "0000000000001"; |
107 | ELSE
|
108 | clk_div2 <= "0000000000000"; |
109 | out_bit_tmp <= NOT out_bit_tmp; |
110 | END IF; |
111 | WHEN "101" => |
112 | cnt <= cnt + "0000000000000000000001"; |
113 | IF (cnt = "1111111111111111111111") THEN |
114 | state <= "110"; |
115 | END IF; |
116 | IF (clk_div2 /= la) THEN |
117 | clk_div2 <= clk_div2 + "0000000000001"; |
118 | ELSE
|
119 | clk_div2 <= "0000000000000"; |
120 | out_bit_tmp <= NOT out_bit_tmp; |
121 | END IF; |
122 | WHEN "110" => |
123 | cnt <= cnt + "0000000000000000000001"; |
124 | IF (cnt = "1111111111111111111111") THEN |
125 | state <= "111"; |
126 | END IF; |
127 | IF (clk_div2 /= xi) THEN |
128 | clk_div2 <= clk_div2 + "0000000000001"; |
129 | ELSE
|
130 | clk_div2 <= "0000000000000"; |
131 | out_bit_tmp <= NOT out_bit_tmp; |
132 | END IF; |
133 | WHEN "111" => |
134 | cnt <= cnt + "0000000000000000000001"; |
135 | IF (cnt = "1111111111111111111111") THEN |
136 | state <= "000"; |
137 | END IF; |
138 | IF (clk_div2 /= duo1) THEN |
139 | clk_div2 <= clk_div2 + "0000000000001"; |
140 | ELSE
|
141 | clk_div2 <= "0000000000000"; |
142 | out_bit_tmp <= NOT out_bit_tmp; |
143 | END IF; |
144 | WHEN OTHERS => |
145 | NULL; |
146 | |
147 | END CASE; |
148 | END IF; |
149 | END IF; |
150 | END PROCESS; |
151 | |
152 | END arch; |
anyone can help me to do it.. or explain it how to call buzzer.vhdl at my rotary switch when i need to turn on my buzzer.
1 | if index=3 then |
2 | J4<='1'; |
3 | --I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON..
|
4 | end if; |
I'm sorry if my english not good.
> and now i need to call buzzer.vhdl at rotary.vhdl With VHDL you are not programming a piece of software, where one module calls another. You are doing a hardware description, and so you must describe a wiring inside a chip (CPLD/FPGA). And therfore you do not call another module, but you instantiate a component and connect it to your top level module. This task is a very common, and so you can find the procedure easily in any VHDL book. > this is my vhdl code for rotary_switch I don't want to read a VHDL decription formatted in such a bad manner. But in there you must do something like that:
1 | architecture Behavioral of main is |
2 | |
3 | signal rotary_a_in: std_logic; |
4 | signal rotary_b_in: std_logic; |
5 | signal rotary_q1: std_logic; |
6 | signal rotary_q2: std_logic; |
7 | signal rotary_in: std_logic_vector(1 downto 0); |
8 | signal rotary_event: std_logic; |
9 | signal rotary_left:std_logic; |
10 | signal delay_rotary_q1:std_logic; |
11 | signal center_flag:std_logic; |
12 | |
13 | component buzzer IS |
14 | PORT ( |
15 | clk : IN std_logic; |
16 | rst : IN std_logic; |
17 | out_bit : OUT std_logic); |
18 | END component; |
19 | |
20 | begin
|
21 | |
22 | buzz : buzzer |
23 | PORT MAP ( clk => clk, rst => rst, out_bit => buzzer_pin); |
24 | END component; |
25 | |
26 | rotary_a_in <= rot_a; |
27 | rotary_b_in <= rot_b; |
But as far i can see, the buzzer code is doing something very stupid in a very difficult way... > or explain it how to call buzzer.vhdl at > my rotary switch when i need to turn on my buzzer. You do not call the code, but you can set a signal to enable buzzing. And then the buzzer will buzz as long as the enable signal is active. BTW: > cnt <= cnt + "0000000000000000000001"; > IF (cnt = "1111111111111111111111") THEN I would do this so: > cnt <= cnt + '1'; > IF (cnt = (others=>'1') THEN Thats much easier to read.