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Forum: FPGA, VHDL & Verilog HELP call VHDL code to other VHDL code


von Vicky V. (viduka)


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Hi.. i need help to call 1 VHDL code to other VHDL code..

i have 2 VHDL code (Rotary_switch and buzzer).. that program work well 
and i can run it at FPGA.. and now i need to call buzzer.vhdl at 
rotary.vhdl. but i dont know how to do that..

this is my vhdl code for rotary_switch
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main is
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port(  clk: in STD_LOGIC;
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    rot_a: in STD_LOGIC;
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    rot_b : in STD_LOGIC;
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    rot_center : in STD_LOGIC;
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    J4 : out  STD_LOGIC;
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    led : out STD_LOGIC_VECTOR (7 downto 0):="00000000");
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end main;
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architecture Behavioral of main is
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signal rotary_a_in: std_logic;
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signal rotary_b_in: std_logic;
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signal rotary_q1: std_logic;
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signal rotary_q2: std_logic;
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signal rotary_in: std_logic_vector(1 downto 0);
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signal rotary_event: std_logic;
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signal rotary_left:std_logic;
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signal delay_rotary_q1:std_logic;
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signal center_flag:std_logic;
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begin
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rotary_a_in <= rot_a;
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rotary_b_in <= rot_b;
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rotary_filter: process(clk)
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begin
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if clk'event and clk='1' then
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rotary_in <= rotary_b_in & rotary_a_in;
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case rotary_in is
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when "00" => rotary_q1 <= '0';
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rotary_q2 <= rotary_q2;
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when "01" => rotary_q1 <= rotary_q1;
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rotary_q2 <= '0';
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when "10" => rotary_q1 <= rotary_q1;
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rotary_q2 <= '1';
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when "11" => rotary_q1 <= '1';
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rotary_q2 <= rotary_q2;
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when others => rotary_q1 <= rotary_q1;
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rotary_q2 <= rotary_q2;
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end case;
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end if;
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end process rotary_filter;
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direction: process(clk)
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begin
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if clk'event and clk='1' then
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delay_rotary_q1 <= rotary_q1;
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if rotary_q1='1' and delay_rotary_q1='0' then
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rotary_event <= '1';
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rotary_left <= rotary_q2;
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else
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rotary_event <= '0';
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rotary_left <= rotary_left;
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end if;
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end if;
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end process direction;
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led_switch: process(clk,rotary_event,rotary_left)
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variable i : integer:=8;
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variable index : integer;
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begin
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if clk'event and clk='1' then
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if rotary_event='1' and rotary_left='0' then --left
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index :=i mod 8;
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led(index)<='1';
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if index=3 then
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J4<='1';
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--I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON..
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end if;
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i:=i+1;
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if i=8 then
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i:=7;
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end if;
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end if;
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if rotary_event='1' and rotary_left='1' then --right
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if i=8 then
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i:=7;
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end if;
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index :=i mod 8;
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led(index)<='0';
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i:=i-1;
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if index=3 then
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J4<='0';
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end if;
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if i=0 then
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i:=1;
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led(0)<='1';
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end if;
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end if;
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end if;
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end process led_switch;
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process(rot_center)
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begin
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if (rot_center='1') then
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center_flag<='1';
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elsif (rot_center='0') then
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center_flag<='0';
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end if;
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end process;
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end Behavioral;

this is my vhdl code for buzzer
1
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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ENTITY buzzer IS
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   PORT (
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      clk  : IN std_logic;   
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      rst  : IN std_logic;   
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      out_bit  : OUT std_logic);   
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END buzzer;
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ARCHITECTURE arch OF buzzer IS
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   SIGNAL clk_div1   :  std_logic_vector(3 DOWNTO 0);  
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   SIGNAL clk_div2   :  std_logic_vector(12 DOWNTO 0); 
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   SIGNAL cnt        :  std_logic_vector(21 DOWNTO 0);  
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   SIGNAL state      :  std_logic_vector(2 DOWNTO 0); 
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   CONSTANT  duo   :  std_logic_vector(12 DOWNTO 0) :="0111011101110";     
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   CONSTANT  lai  :  std_logic_vector(12 DOWNTO 0) := "0110101001101";    
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   CONSTANT  mi   :  std_logic_vector(12 DOWNTO 0) := "0101111011010";    
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   CONSTANT  fa    :  std_logic_vector(12 DOWNTO 0) := "0101100110001";    
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   CONSTANT  suo   :  std_logic_vector(12 DOWNTO 0) := "0100111110111";    
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   CONSTANT  la    :  std_logic_vector(12 DOWNTO 0) := "0100011100001";    
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   CONSTANT  xi    :  std_logic_vector(12 DOWNTO 0) := "0011111101000";    
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   CONSTANT  duo1   :  std_logic_vector(12 DOWNTO 0) := "0011101110111";   
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   SIGNAL out_bit_tmp :std_logic; 
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BEGIN
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   out_bit<=out_bit_tmp;
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   PROCESS(clk,rst)
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   BEGIN
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       IF (NOT rst = '1') THEN
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         clk_div1 <= "0000";    
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      ELSif(clk'event and clk='1')then
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         IF (clk_div1 /= "1100") THEN
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            clk_div1 <= clk_div1 + "0001";    
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         ELSE
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            clk_div1 <= "0000";    
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         END IF;
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      END IF;
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   END PROCESS;
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   PROCESS(clk,rst)
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   BEGIN
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      IF (NOT rst = '1') THEN
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         clk_div2 <= "0000000000000";    
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         state <= "000";    
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         cnt <= "0000000000000000000000";    
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         out_bit_tmp <= '0';    
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      ELSif(clk'event and clk='1')then
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         IF (clk_div1 = "1001") THEN
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            CASE state IS
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               WHEN "000" =>
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "001";    
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                        END IF;
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                        IF (clk_div2 /= duo) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "001" =>  
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "010";    
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                        END IF;
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                        IF (clk_div2 /=lai) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "010" => 
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "011";    
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                        END IF;
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                        IF (clk_div2 /=mi) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "011" =>  
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "100";    
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                        END IF;
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                        IF (clk_div2 /=fa) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "100" =>   
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "101";    
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                        END IF;
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                        IF (clk_div2 /=suo) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "101" => 
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "110";    
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                        END IF;
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                        IF (clk_div2 /= la) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "110" => 
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "111";    
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                        END IF;
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                        IF (clk_div2 /= xi) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN "111" => 
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                        cnt <= cnt + "0000000000000000000001";    
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                        IF (cnt = "1111111111111111111111") THEN
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                           state <= "000";    
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                        END IF;
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                        IF (clk_div2 /= duo1) THEN
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                           clk_div2 <= clk_div2 + "0000000000001";    
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                        ELSE
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                           clk_div2 <= "0000000000000";    
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                           out_bit_tmp <= NOT out_bit_tmp;    
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                        END IF;
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               WHEN OTHERS =>
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                        NULL;
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            END CASE;
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         END IF;
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      END IF;
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   END PROCESS;
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END arch;

anyone can help me to do it.. or explain it how to call buzzer.vhdl at 
my rotary switch when i need to turn on my buzzer.
1
if index=3 then
2
J4<='1';
3
--I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON..
4
end if;

I'm sorry if my english not good.

von lkmiller (Guest)


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0 useful
not useful
> and now i need to call buzzer.vhdl at rotary.vhdl
With VHDL you are not programming a piece of software, where one 
module calls another. You are doing a hardware description, and so you 
must describe a wiring inside a chip (CPLD/FPGA). And therfore you do 
not call another module, but you instantiate a component and connect it 
to your top level module.
This task is a very common, and so you can find the procedure easily in 
any VHDL book.

> this is my vhdl code for rotary_switch
I don't want to read a VHDL decription formatted in such a bad manner. 
But in there you must do something like that:
1
architecture Behavioral of main is
2
3
signal rotary_a_in: std_logic;
4
signal rotary_b_in: std_logic;
5
signal rotary_q1: std_logic;
6
signal rotary_q2: std_logic;
7
signal rotary_in: std_logic_vector(1 downto 0);
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signal rotary_event: std_logic;
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signal rotary_left:std_logic;
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signal delay_rotary_q1:std_logic;
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signal center_flag:std_logic;
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component buzzer IS
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   PORT (
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      clk  : IN std_logic;   
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      rst  : IN std_logic;   
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      out_bit  : OUT std_logic);   
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END component;
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begin
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buzz : buzzer 
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      PORT MAP ( clk  => clk, rst => rst, out_bit => buzzer_pin);   
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END component;
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rotary_a_in <= rot_a;
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rotary_b_in <= rot_b;

But as far i can see, the buzzer code is doing something very stupid in 
a very difficult way...

> or explain it how to call buzzer.vhdl at
> my rotary switch when i need to turn on my buzzer.
You do not call the code, but you can set a signal to enable buzzing. 
And then the buzzer will buzz as long as the enable signal is active.

BTW:
>              cnt <= cnt + "0000000000000000000001";
>              IF (cnt = "1111111111111111111111") THEN
I would do this so:
>              cnt <= cnt + '1';
>              IF (cnt = (others=>'1') THEN
Thats much easier to read.

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