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Hi.. i need help to call 1 VHDL code to other VHDL code.. i have 2 VHDL code (Rotary_switch and buzzer).. that program work well and i can run it at FPGA.. and now i need to call buzzer.vhdl at rotary.vhdl. but i dont know how to do that.. this is my vhdl code for rotary_switch
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity main is port( clk: in STD_LOGIC; rot_a: in STD_LOGIC; rot_b : in STD_LOGIC; rot_center : in STD_LOGIC; J4 : out STD_LOGIC; led : out STD_LOGIC_VECTOR (7 downto 0):="00000000"); end main; architecture Behavioral of main is signal rotary_a_in: std_logic; signal rotary_b_in: std_logic; signal rotary_q1: std_logic; signal rotary_q2: std_logic; signal rotary_in: std_logic_vector(1 downto 0); signal rotary_event: std_logic; signal rotary_left:std_logic; signal delay_rotary_q1:std_logic; signal center_flag:std_logic; begin rotary_a_in <= rot_a; rotary_b_in <= rot_b; rotary_filter: process(clk) begin if clk'event and clk='1' then rotary_in <= rotary_b_in & rotary_a_in; case rotary_in is when "00" => rotary_q1 <= '0'; rotary_q2 <= rotary_q2; when "01" => rotary_q1 <= rotary_q1; rotary_q2 <= '0'; when "10" => rotary_q1 <= rotary_q1; rotary_q2 <= '1'; when "11" => rotary_q1 <= '1'; rotary_q2 <= rotary_q2; when others => rotary_q1 <= rotary_q1; rotary_q2 <= rotary_q2; end case; end if; end process rotary_filter; direction: process(clk) begin if clk'event and clk='1' then delay_rotary_q1 <= rotary_q1; if rotary_q1='1' and delay_rotary_q1='0' then rotary_event <= '1'; rotary_left <= rotary_q2; else rotary_event <= '0'; rotary_left <= rotary_left; end if; end if; end process direction; led_switch: process(clk,rotary_event,rotary_left) variable i : integer:=8; variable index : integer; begin if clk'event and clk='1' then if rotary_event='1' and rotary_left='0' then --left index :=i mod 8; led(index)<='1'; if index=3 then J4<='1'; --I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON.. end if; i:=i+1; if i=8 then i:=7; end if; end if; if rotary_event='1' and rotary_left='1' then --right if i=8 then i:=7; end if; index :=i mod 8; led(index)<='0'; i:=i-1; if index=3 then J4<='0'; end if; if i=0 then i:=1; led(0)<='1'; end if; end if; end if; end process led_switch; process(rot_center) begin if (rot_center='1') then center_flag<='1'; elsif (rot_center='0') then center_flag<='0'; end if; end process; end Behavioral; |
this is my vhdl code for buzzer
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY buzzer IS PORT ( clk : IN std_logic; rst : IN std_logic; out_bit : OUT std_logic); END buzzer; ARCHITECTURE arch OF buzzer IS SIGNAL clk_div1 : std_logic_vector(3 DOWNTO 0); SIGNAL clk_div2 : std_logic_vector(12 DOWNTO 0); SIGNAL cnt : std_logic_vector(21 DOWNTO 0); SIGNAL state : std_logic_vector(2 DOWNTO 0); CONSTANT duo : std_logic_vector(12 DOWNTO 0) :="0111011101110"; CONSTANT lai : std_logic_vector(12 DOWNTO 0) := "0110101001101"; CONSTANT mi : std_logic_vector(12 DOWNTO 0) := "0101111011010"; CONSTANT fa : std_logic_vector(12 DOWNTO 0) := "0101100110001"; CONSTANT suo : std_logic_vector(12 DOWNTO 0) := "0100111110111"; CONSTANT la : std_logic_vector(12 DOWNTO 0) := "0100011100001"; CONSTANT xi : std_logic_vector(12 DOWNTO 0) := "0011111101000"; CONSTANT duo1 : std_logic_vector(12 DOWNTO 0) := "0011101110111"; SIGNAL out_bit_tmp :std_logic; BEGIN out_bit<=out_bit_tmp; PROCESS(clk,rst) BEGIN IF (NOT rst = '1') THEN clk_div1 <= "0000"; ELSif(clk'event and clk='1')then IF (clk_div1 /= "1100") THEN clk_div1 <= clk_div1 + "0001"; ELSE clk_div1 <= "0000"; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (NOT rst = '1') THEN clk_div2 <= "0000000000000"; state <= "000"; cnt <= "0000000000000000000000"; out_bit_tmp <= '0'; ELSif(clk'event and clk='1')then IF (clk_div1 = "1001") THEN CASE state IS WHEN "000" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "001"; END IF; IF (clk_div2 /= duo) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "001" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "010"; END IF; IF (clk_div2 /=lai) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "010" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "011"; END IF; IF (clk_div2 /=mi) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "011" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "100"; END IF; IF (clk_div2 /=fa) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "100" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "101"; END IF; IF (clk_div2 /=suo) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "101" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "110"; END IF; IF (clk_div2 /= la) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "110" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "111"; END IF; IF (clk_div2 /= xi) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN "111" => cnt <= cnt + "0000000000000000000001"; IF (cnt = "1111111111111111111111") THEN state <= "000"; END IF; IF (clk_div2 /= duo1) THEN clk_div2 <= clk_div2 + "0000000000001"; ELSE clk_div2 <= "0000000000000"; out_bit_tmp <= NOT out_bit_tmp; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; END PROCESS; END arch; |
anyone can help me to do it.. or explain it how to call buzzer.vhdl at my rotary switch when i need to turn on my buzzer.
if index=3 then J4<='1'; --I WANT CALL MY BUZZER.VHDL IN HERE. SO ITS MEAN WHEN INDEX=3 I WANT MY BUZZER ON.. end if; |
I'm sorry if my english not good.
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> and now i need to call buzzer.vhdl at rotary.vhdl With VHDL you are not programming a piece of software, where one module calls another. You are doing a hardware description, and so you must describe a wiring inside a chip (CPLD/FPGA). And therfore you do not call another module, but you instantiate a component and connect it to your top level module. This task is a very common, and so you can find the procedure easily in any VHDL book. > this is my vhdl code for rotary_switch I don't want to read a VHDL decription formatted in such a bad manner. But in there you must do something like that:
architecture Behavioral of main is signal rotary_a_in: std_logic; signal rotary_b_in: std_logic; signal rotary_q1: std_logic; signal rotary_q2: std_logic; signal rotary_in: std_logic_vector(1 downto 0); signal rotary_event: std_logic; signal rotary_left:std_logic; signal delay_rotary_q1:std_logic; signal center_flag:std_logic; component buzzer IS PORT ( clk : IN std_logic; rst : IN std_logic; out_bit : OUT std_logic); END component; begin buzz : buzzer PORT MAP ( clk => clk, rst => rst, out_bit => buzzer_pin); END component; rotary_a_in <= rot_a; rotary_b_in <= rot_b; |
But as far i can see, the buzzer code is doing something very stupid in a very difficult way... > or explain it how to call buzzer.vhdl at > my rotary switch when i need to turn on my buzzer. You do not call the code, but you can set a signal to enable buzzing. And then the buzzer will buzz as long as the enable signal is active. BTW: > cnt <= cnt + "0000000000000000000001"; > IF (cnt = "1111111111111111111111") THEN I would do this so: > cnt <= cnt + '1'; > IF (cnt = (others=>'1') THEN Thats much easier to read.
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