cooler <= cooler - 1;  -- per .5s
Do you expect the synthesizer to interpret your comments?
Let me say: thats a stupid code that will never work, but you already 
found the actual problem:
> I don't know how to do the clock dividers
But you ended up in the wrong direction:
> so I am just working on the increase/ decrease of the value

PittyJ already gave a hint: every time (at least all the times > 10ns) 
on a FPGA is based on a counter. So you must implement a counter, that 
counts to  half a second. And with that counter you can increase you 
cooler-value...

> I commented out every counter except one to test it alone
That here:
      cooler <= cooler - 1;  -- per .5s
is not a counter, because there is no clock involved! Its just a very 
unuseful and unwanted thing called "combinational loop" or 
"combinatorial loop" (try these two phrases with google).

I have a clock sorry to not include it even with clock it repeats same 
number over and over

Architecture logic of Coolertemp is
  signal cooler: std_logic_vector (6 downto 0);
 
  begin
  process (t_set, c_temp, d,cooler,clk)
   
begin
 
  cooler <= c_temp;
 
  if(d='0')then
    -- cooler <= cooler + "0000001"; --per two minutes (120s)
   
      if(c_temp>t_set and clk' event and clk = '1') then
        c <= '1';
 
      cooler <= cooler - 1;  --per .5s
    
    end if;
     

end

This is a EXTREMELY UNUSUAL description of a clock enable. Have a look 
at all the other VHDL code around the world. Doing it the same way 
will look more like this:

1

process (clk) begin

2

  if rising_edge(clk) then

3

     if(d='0' and cooler >t_set) then

4

        c <= '1';

5

        cooler <= cooler - 1;  --per .5s

6

     end if;

7

  end if;

8

end process;

> I have a clock sorry to not include it even with clock it repeats
> same number over and over
And how does that look like? Do you do a simulation (recommended) or do 
you test it on hardware (unusual).