Hello to all,
I am writing a VHDL code in ISE 9.2, using Modelsim PE 10 Student
Edition for simulation. I want to use the sll function in order to
rotate a std_logic_vector. When I synthesize the following code with ISE
I do not get any errors. But when I am trying to simulate my program
using Modelsim, I get only "U" signals. Could somebody tell me what I am
doing wrong?
Thanks in advance
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.numeric_std.ALL;
entity shifter is
Port ( Bus_B : in STD_LOGIC_VECTOR (31 downto 0);
shamt_in : in STD_LOGIC_VECTOR (4 downto 0);
shift_out : out STD_LOGIC_VECTOR (31 downto 0));
end shifter;
architecture Behavioral of shifter is
signal B_32 : bit_vector(31 downto 0);
signal temp : std_logic_vector(31 downto 0);
begin
process ( Bus_B, shamt_in)
begin
B_32 <= to_bitvector(Bus_B) sll conv_integer(shamt_in);
temp <= to_stdlogicvector(B_32);
end process;
shift_out <= temp;
end Behavioral;