vhdl/verilog code for interfacing DDR3 SDRAM to virtex6 or spartran6 fpga

ya virtex and spartan by mistake i typed dat....
ok thank you

Why do you want to write this by your own? You can use the Xilinx MIG 
from the ISE Core Generator.

actually in my project there is a use with this DDR3 so i thought of 
writing.
Ok then can u say me any website or any book for understanding DDR3 and 
their interfacing with fpga's......
Thank you.

Check below link ..
http://opencores.org/project,sdram_controller

HI can any1 say me how to generate a code for DDR3 SDRAM controller from 
MIG core generator of Xilinx.
     I want to write the data to DDR3 SDRAM and i want to Read the data 
from DDR3 SDRAM  for this i have visited opencores i got Synthesizable 
Bfm but is that sufficient for doing this iam unable to get 
clarification. Can any1 please clarify.

    Thank you in advance

Hi can any 1 help me how to write verilog program for interfacing ddr3 
memory to an fpga.
What is the difference between interfacing a ddr3 controller and ddr3 
memory to fpga.
Suppose if we buy a ddr3sdram chip then now if we want to interface that 
to an fpga then How can i proceed for this please.
Thank you.

Hi i have code for this but when iam trying to implementing it shows 
some errors and also. Can any1 please check out this and say me wat to 
do or make some some corrections please

Ya but for controller can v generate from MIG or what to do iam really 
not understanding what to do. please suggest me....

can you check out this code and suggest me....