vhdl to verilog convert

Hi,

I need to convert this vhdl function in to verilog

FUNCTION EXT (A: STD_LOGIC_VECTOR; SIZE: NATURAL) RETURN 
STD_LOGIC_VECTOR IS
VARIABLE RS: STD_LOGIC_VECTOR (SIZE-1 DOWNTO 0);
VARIABLE TMP: STD_LOGIC_VECTOR (A'length-1 DOWNTO 0);
CONSTANT MSB: natural := min(A'length, SIZE) - 1;
BEGIN
TMP := TO_X01 (A);
RS := (others => '0');
RS(MSB DOWNTO 0) := TMP(MSB DOWNTO 0);
RETURN RS;
END;