Hi I got this VHDL program that opens the lock when the pin code is correct. I was provided with the testbench and I have written the lock code. But it doesn't seem to work. Maybe someone could see what could be wrong.
What happens if you take current_state out of the process sensitivity list? input should be the ony one because otherwise it will run in a endless loop.
> But it doesn't seem to work. How do you see that? Indeed there are several problems inside the code:
-- a little bit curious combinational and clocked process... :-o process(clock, reset) begin -- a clocked part if (reset='1') then current_state <= 0; elsif (clock'event and clock='1') then current_state <= next_state; end if; -- and a combinational part if current_state = 8 then -- current_state is missing in the sensitivity list! output <= '1'; else output <= '0'; end if; end process;
And this is, why the thing never will work reliably on hardware:
process(current_state,input) begin case current_state is when 0 => if input = "0000000001" then -- input is not synchronized to clock!
Every asynchronous input MUST be synchronized to the internal clock by 2 flipflops. Try this with google translator: http://www.lothar-miller.de/s9y/categories/35-Einsynchronisieren http://translate.google.de/translate?sl=de&tl=en&js=n&prev=_t&hl=de&ie=UTF-8&layout=2&eotf=1&u=http%3A%2F%2Fwww.lothar-miller.de%2Fs9y%2Fcategories%2F35-Einsynchronisieren&act=url It gives a crude translation, but maybe you will get the idea...
I tried removing the input from the sensitivity list but it doesn't change the graph. I know it doesn't work from the graph, when I test it. Some questions: What do I need to include in the sensitivity list? All things I use in the processes, in my case current_state, next_state, input etc? This isn't the case in many examples. I tried reading the article, however I can't grasp most of those terms and the translator isn't helping that much. Maybe I should use something like "wait on clock until clock = '1'".
> What do I need to include in the sensitivity list? Keep one thing in mind: the sensitivity list is ONLY for simulation. The synthesizer ignores this list! So the list must contain every signal that requires a calculation of the process in simulation. In the case of this one process(clock, reset) the current_state is missing (due to the curious clocked-and-combinational style). In this process process(current_state,input) the list is complete. At a change of current_state or a change of input the process must be calculated. > I tried reading the article, however I can't grasp most of those terms > and the translator isn't helping that much. Its a long way to go... :-( > Maybe I should use something like "wait on clock until clock = '1'". I prefer this: wait until rising_edge(clock); And so ALL of my processes are concurrent, and i do not have a current_state and a next_state. I have just the state... So my description would look like this:
process begin wait until rising_edge(clock); case current_state is when 0 => if input = "0000000001" then state <= 1; end if; when 1 => if input = "0000000000" then state <= 2; else state<= 0; end if; when 2 => if input = "0000000001" then state <= 3; else state < =0 ; end if; when 3 => if input = "0000001000" then state <= 4; else state <= 0; end if; : : : when 7 => if input = "0000001001" then state <= 8; else state <= 0; end if; when 8 => state <= 0; end case; end process; output <= '1' when state=8 else '0';
One word to the when others
signal next_state, current_state: integer range 0 to 8; : : when 8 => next_state <= 0; when others => -- ignored! next_state <= 0;
The states only can have the values 0 to 8. Thats the way they are defined! When you use all of these values explicitly the are no remainings for when others. These last path is simply ignored and therefore needless.
I modified my code, now it gives these errors. The rising_edge line gives me this error: Prefixed name 'rising_edge' is not a 1 dimensional array or a function or contains a bad suffix (index/slice/selected-name). Also there is another error, the simulator fails to connect: Unresolved signal 'state' has more than one source I also tried with my old code, used the rising_edge function, but it too doesn't like it.
> Unresolved signal 'state' has more than one source That says: you are driving the signal e.g. from more than 1 process or from a process and also concurrent... > I modified my code, now it gives these errors. Why did you add a process? With my code you have only ONE process. And this one is clocked. This design style is a little bit different to the "usual" style you can find in most ancient books. Try to search for a "one process fsm". Get rid of this (its already in the FSM process) nd your design will run:
process(clock, reset) begin if (reset='1') then state <= 0; elsif (clock'event and clock='1') then state <= state; end if; end process;
BTW: did you think a little of anything when you wrote that code? Wich every clock you assign state to state. What should this be good for? > I also tried with my old code, used the rising_edge function, but it > too doesn't like it. You must not TRY, you must UNDERSTAND...
Thank you for your help. I feel blindfolded when writing VHDL (the asynchronous stuff), I know? the syntax but the inner workings might go over my head. The code was "compiled" from different examples(with modifications of course), so I did my best when knowing very little. Usually I am an avid googler, but it seems that there is very little information about VHDL even forums are hard to find. I still added this other process, because there is the reset ?variable, even though the state<=state is useless. I removed the other process and it still gives me those errors. Also, the rising_edge(clock) still gives me the same error. Perhaps it's a simulator specific thing. It compiles with "wait on clock until clock = '1'", but the graph doesn't show me anything. The reset variable is 1 in graph. I want to understand.