Hi This is a beginner problem. I don't know how to compare these 2 types. I got overload error when trying to compare
1 | if keypad(1) = 1 then |
2 | next_state <= 1; |
keypad is a bit_vector(9 downto 0).
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Forum: FPGA, VHDL & Verilog VHDL bit_vector overload problemHi This is a beginner problem. I don't know how to compare these 2 types. I got overload error when trying to compare
keypad is a bit_vector(9 downto 0). keypad(1) = '1' beim ganzen Keypad wäre es dann keypad = "xxxxxxxxxx" wobei x entweder eine 1 oder eine 0 sein kann. Also einzelne Bitwerte in ' ' und mehrere in " ". thanks, I saw my error. But my program won't work still. I added it into the attachment. Sorry for the german ...
Ok you wrote
when 0 =>
if input = "0000000001" then
next_state <= 1;
else
next_state <= 0;
end if;
so it depends on the input - how ist the input connected? How long is
the input provided? I mean, if the input is only for a very short time
not 0, then it is most of the time 0. And then your next_state = 2 and
also current_state, because current_state is updated every clock.
Edit:
The process depends on current_state and input.
So if we step along, say current_state=0 and input= "0000000001" then
the process assigns next_state to 1.
BUT: in the next clockcycle, current_state is updated to next_state, in
this case to 1.
Because current_state ist updated, the process runs again and now with
input still "0000000001" it goes to
when 1 =>
and because input is not "0000000000" the next_state = 0.
And so on. Now current_state is updated to 0 and it begins again even if
the input doesn't change.
I don't know if it helps, but i would test if it works woth only input
in the sensitivity list
process(input)
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