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Forum: FPGA, VHDL & Verilog how to generate a RANDOM NUMBER in VHDL


how to generate a RANDOM NUMBER in VHDL
von deepak s. (dksagra)

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hi,
please tell me how to generate a RANDOM NUMBER in VHDL

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Re: how to generate a RANDOM NUMBER in VHDL
von Christoph S. (mixer)

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Hi,

if you just simulate a VHDL code you can use the UNIFORM procedure, but 
if you want to use random numbers on real Hardware you may could use a 
linear feedback shift register.

Greets

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Re: how to generate a RANDOM NUMBER in VHDL
von deepak s. (dksagra)

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if have to use it on HARDWARE..

Best Regards

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Re: how to generate a RANDOM NUMBER in VHDL
von user (Guest)

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you can use a lfsr
http://en.wikipedia.org/wiki/Linear_feedback_shift_register

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Re: how to generate a RANDOM NUMBER in VHDL
von Hotte (Guest)

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This is no random number. These numbers are dedicated and only hard to 
estimate. real random numbers can only ge generated from non dedicated 
information sources like temprature, radiation and such thigs.

you have to scan your environment and bring them into your system with 
an ADC influencing random number generators perhaps.

you can find an approch here in this forum at:
http://www.mikrocontroller.net/articles/Digitaler_Zufallszahlengenerator_in_VHDL 
(german only)

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Re: how to generate a RANDOM NUMBER in VHDL
von Raghavendra B. (raghavendra_b98)

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Random number in VHDL in opencore project.

http://opencores.org/project,rng_lib

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Re: how to generate a RANDOM NUMBER in VHDL
von patu (Guest)

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Do you need the random for security eg. crypto ?

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Re: how to generate a RANDOM NUMBER in VHDL
von Raghavendra B. (raghavendra_b98)

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I don't no about security.

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