Hi everybody,
I'm new to VHDL and I'm doing a project for uni. I'm having problems
instatiating a component in a project: I'm trying to build a slow
counter by using a clock divider and a 8-bit counter. I'm sure both the
counter and the divider work, taken separately. Now, I want to reuse the
code for the counter, instatiate the freq div to obtain a "slow counter"
driven by the clock. However, the code below yields "output pins stuck
to GND or VCC". Can anyone see why ?
Thanks
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity slow_cnt2 is
port (
clock: in std_logic;
rst: in std_logic;
Q: out std_logic_vector ( modulus-1 downto 0)
);
end slow_cnt2;
architecture bhv of slow_cnt2 is
signal tcount: std_logic_vector (modulus-1 downto 0); -- inner
counter
signal slowclk : std_logic;
component clk_div is
port (
clk: in std_logic;
clkout : out std_logic);
end component;
begin -- bhv
divider : clk_div port map (
clk => clock,
clkout => slowclk);
count: process (slowclk, rst)
begin -- process count
if rst = '0' then -- asynchronous reset
(active low)
tcount <= (others => '0');
elsif slowclk'event and slowclk = '1' then
tcount <= tcount + '1';
end if;
end process count;
Q <= tcount;
end bhv;