Verilog Hardware primitives giving odd output

I am a student just starting with Verilog and am trying to create a 
module to take all the numbers between 0 and 63 and then modulo them by 
three and five.

I am trying to do it with a pair of hardware primitives, and the modulo 
three works, but trying to modulo by other numbers mysteriously does 
not. I have tried 2/3/4/5/10 now and they have all given me very odd 
output in both the simulator and on the DE2 board I am working with.

Things I have tried as well: using only one primitive in the top level, 
separate inputs for the different primitives, changing the amount of 
time in the test bench, and re-writing the entire truth table. I get the 
same wrong outputs every time regardless of what I do.

The zip file included has text files for the outputs of all the 
different modulos, and the source files for the top level module, the 
test bench, and all the different modulos I have created.