Hi all!! We're having some problems with a finite-state machine in VHDL. When a button is pressed, it is supposed to go to its corresponding state, but the only thing we obtain in the simulation is that, if we press the BTN1 button, we go to the "0001" state, all right, but after that, if we press any other button, although button BTN1 is not pressed, the state machine goes to the "0001" state, ergo, the state of the BTN1 button. Attached you have the behavioral source of our finite-state machine. Hope you can help us. P.S. We are using Xilinx ISE 11.4 Design Suite. Thank you all!!
external signals like buttons have to be synchronized-in. so register the button input with two flipflops.
> external signals like buttons have to be synchronized-in. This hint is correct, but it doen't reflect the actual problem! Because as far as I see even the simulation doesn't work as expected: >>> but the only thing we obtain in the simulation And so the question is: How do yoou see the fail? How does the testbench look like? Can you post the testbench also, or at least a screenshot of the waveform? BTW There's much too much in the sensitivity list of this process:
U: PROCESS (CLK, RST, BTN1, BTN2, BTN3, BTN4, BTN5, BTN6, BTN7) BEGIN IF (RST='1') then E<="0000"; ELSIF (rising_edge(CLK)) then
This would be enough:
U: PROCESS (CLK, RST) BEGIN IF (RST='1') then E<="0000"; ELSIF (rising_edge(CLK)) then