Thanks for the response

> you habe to define a data-type and then use this type
Of course you will have to do this type definition inside a package. And 
then include this package in your vhdl file...

So it looks like this:

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library IEEE;

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use IEEE.STD_LOGIC_1164.all;

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package mytypes is

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   type mytype is array(0 to 31) of std_logic_vector(31 downto 0);

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end mytypes;

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-- and then (may be in another file)

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use work.mytypes.all;

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entity test is

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    Port ( i : in  mytype;

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           o : out mytype

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          );

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end test;

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:

Hi Lothar,
The following code is what I have done.

=====================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;

package block_arrays is
type block_array is array (0 to 31) of std_logic_vector(31 downto 0);
end block_arrays;
=====================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.block_array.all;

entity ram_mux_32_1_nbit is
generic(n:integer:=32);
port(  sel: in std_logic_vector(4 downto 0);
  x: in block_array;
  y: out std_logic_vector((n-1)downto 0));
end ram_mux_32_1_nbit;

architecture Behavioral of ram_mux_32_1_nbit is

begin
with sel select
  y <= x(0) when "00000", (others => 'Z'),
             x(1) when "00001", (others => 'Z'),
             ..........
             x(31) when "11111", (others => 'Z'),
       (others => 'Z') when others;
end Behavioral;

=====================================================================

The testbench looks like this though - x is seen as a single array

 COMPONENT ram_mux_32_1_nbit
    PORT(
         sel : IN  std_logic_vector(4 downto 0);
         x : IN  std_logic_vector(0 to 31);
         y : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;

======================================================================

When I try to give x a value in the testbench;-

x(0) <= "00000000000000000000000000000001";
.....
x(31) <= "10000000000000000000000000000000";

.....I get the following error:-
Type std_ulogic does not match with a string literal.

Would this be because of the component declaration only being seen as a 
std_logic_vector?

> Would this be because of the component declaration only being seen
> as a std_logic_vector?
Yes.
> The testbench looks like this though - x is seen as a single array
So, it is YOU, who wrote a WRONG port definiton inside the test bench. 
And if the toolchain did it, it was YOU, who did NOT CORRET it. Ports 
other then std_logic is something the "semi-automatic" tcl-script in ISE 
can't cope up with! Its YOUR job to get the correct components in your 
upper-level modules (like a testbench).


To keep things short:
The component in the testbench must be the same as the entity! So you 
must edit to get the same ports:

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 COMPONENT ram_mux_32_1_nbit

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    PORT( sel: in std_logic_vector(4 downto 0);

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          x: in block_array;

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          y: out std_logic_vector((n-1)downto 0)

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        );

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 end component;

I thought the testbench software was gospel - didn't realise they could 
be wrong also. Thanks again!