# Forum: FPGA, VHDL & Verilog any value conversion to 32 bit vector form in vhdl.please help

Rate this post
 0 ▲ useful ▼ not useful
hi, please help me out...

i have a constant value let A:=9
now i have to convert into digital form...
as we know in digital we can write this 00000000000000000000000000001001
for 32 bit data...
another example i have A:=34
we can write this 00000000000000000000000100010

i want this type of conversion (any number into 32 bit vector form)in
VHDL...
please help me out..its too urgent

Rate this post
 0 ▲ useful ▼ not useful
Try this:
 1 library IEEE;  2 use IEEE.STD_LOGIC_1164.ALL;  3 use IEEE.NUMERIC_STD.ALL;  4 :  5 signal vector std_logic_vector(31 downto 0);  6 :  7 vector <= std_logic_vector(to_unsigned(34,32)); -- here your value 34 is converted to a 32 bit vector 


BTW:
WHERE does this value come from?
I ask this because I think you asked the wrong question...

Rate this post
 0 ▲ useful ▼ not useful
thank you so much...
its a long program...
if u want to have a look than i can send...but u understand my logic
right...

but the value of A changes very instant of time...
cant we put directly A inplace of 34
means
vector <= std_logic_vector(to_unsigned(A,32));
like wise...

regards

Rate this post
 0 ▲ useful ▼ not useful
If A is an integer, then yes.

Rate this post
 0 ▲ useful ▼ not useful
please tell me one thing more...if vector define by you, is variable..

means vector is not signal,its variable..can this convergence is
possible..

regards

Rate this post
 0 ▲ useful ▼ not useful
> vector is not signal,its variable..
What do you mean?
Mark with a x:
[ ] the vector is a variable.
[ ] the input value A is variable, it changes.

> if u want to have a look than i can send...
Pls post it here as a *.vhdl file attachment.

Rate this post
 0 ▲ useful ▼ not useful
sending the word file document...
error at the last page...at K_temp

Rate this post
 0 ▲ useful ▼ not useful
> Pls post it here as a *.vhdl file attachment.
Try it again as *.vhd  or *.vhdl, NOT AS a Microsoft Word *.docx file!

Rate this post
 0 ▲ useful ▼ not useful
ok...
i am sending the VHD extension file...

regards

Rate this post
 0 ▲ useful ▼ not useful
this is zip file, containing everything...

Rate this post
 0 ▲ useful ▼ not useful
> .docx
> .ise
> .rar
> zip
I cannot help you with those files, because I'm on a smartphone and
can't open either one of them...

So just attach the according *.vhd or *.vhdl file. Is it that difficult?

Rate this post
 0 ▲ useful ▼ not useful
ok...
this is the file extension .vhd..
problem is at the K_temp

thanks

regards

Rate this post
 0 ▲ useful ▼ not useful
 1 --error is here-"Operator must have constant operands or first operand must be power of 2  2 K_temp := "0100000000000000000000000000000000" /A ; 
Oooops, a divider. Is this design for a FPGA?

You can simulate a division easily.
But if you want it to run on real hardware, you will get immediately
into trouble, if the divisor isn't a power of 2 (like 2, 4, 8, 16,
32...).

Because if the divisor is a power of 2, then the division is just a
different wiring inside the FPGA. Thats easy, and its done by the
synthesizer on its won.

If the divisor is not a power of 2, then the division gets fairly
complex. You then usually involve a divider-core, plus you will have to
read a manual of at least 20 pages...   :-o

BTW:
 1 Use IEEE .numeric_std .All ; -- take his one  2 3 use IEEE.std_logic_signed.all; -- or those old osolete ones here  4 --use IEEE.std_logic_unsigned.all;  5 use IEEE.std_logic_arith.all;  6 7  -- but never all of them together!!! 

BTW2:
 1 -- ***********************  2 --* Begin main process . *  3 -- ***********************  4 Begin  5 Process ( z_position , reset ) Is 
1. There is no "main process". Every process has the very same
proirity, because every process will be synthesized to hardware.

2. The reset is absolutely unnecessary. Because even with reset='1' the
reset-values of x and P will be overwritten immediately in the first two
lines after the "end if;".

BTW3:
 1 x :=  2 ("00000000000000010000000000000000",  3 "00000000000000010000000000000000"); 
For better readability try this:
 1 x := (x"00010000",x"00010000"); 
Or this:
 1 x := (to_signed(65536,32),to_signed(65536,32)); 

BTW4:
>>> Begin main process
This whole design looks like you are "thinking in software", this will
not lead to a solution for a language that "describes hardware"!

Rate this post
 0 ▲ useful ▼ not useful
So what to do now?
should i use ipcore?
or one thing is in my mind, tell me is it possible
in K_temp := "0100000000000000000000000000000000" /A ;
first i convert "0100000000000000000000000000000000" into integer
and then convert A into integer..
then divide both bcoz they are in integer now..
after that the resultant of the divison be converted back into signed...

thanks

best regards

Rate this post
 0 ▲ useful ▼ not useful
> or one thing is in my mind, tell me is it possible ....
> then divide both bcoz they are in integer now..
Absolutely NO.
Because casting and converting does not change one thing at the fact:
you want to do a division.

You're tricking around and hoping for a hidden way.
That will not work here...

> should i use ipcore?
I think you will have to. And: read ALL of the documentation.

Rate this post
 0 ▲ useful ▼ not useful
thanks a lot....

i would go for ipcore..if i have any problem, i know who can help me
now...

best reagrds....

Rate this post
 0 ▲ useful ▼ not useful
thanks...
i have implemented the divisor core...
the whole program is working well now...

thanks a ton really..

regards...

Rate this post
 0 ▲ useful ▼ not useful
> the whole program is working well now...
Once more (the last time): you do not program a FPGA.
You're writing a hardware description for a FPGA.

> thanks a ton really..
You're welcome.

Rate this post
 0 ▲ useful ▼ not useful
Yes...
now implementing on FPGA...

Regards...

• $formula (LaTeX syntax)$