hi, please help me out... i have a constant value let A:=9 now i have to convert into digital form... as we know in digital we can write this 00000000000000000000000000001001 for 32 bit data... another example i have A:=34 we can write this 00000000000000000000000100010 i want this type of conversion (any number into 32 bit vector form)in VHDL... please help me out..its too urgent
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; : signal vector std_logic_vector(31 downto 0); : vector <= std_logic_vector(to_unsigned(34,32)); -- here your value 34 is converted to a 32 bit vector
BTW: WHERE does this value come from? And whats your actual problem? I ask this because I think you asked the wrong question...
thank you so much... its a long program... if u want to have a look than i can send...but u understand my logic right... but the value of A changes very instant of time... cant we put directly A inplace of 34 means vector <= std_logic_vector(to_unsigned(A,32)); like wise... regards
If A is an integer, then yes.
please tell me one thing more...if vector define by you, is variable.. means vector is not signal,its variable..can this convergence is possible.. regards
> vector is not signal,its variable.. What do you mean? Mark with a x: [ ] the vector is a variable. [ ] the input value A is variable, it changes. > if u want to have a look than i can send... Pls post it here as a *.vhdl file attachment.
sending the word file document... error at the last page...at K_temp
> Pls post it here as a *.vhdl file attachment. Try it again as *.vhd or *.vhdl, NOT AS a Microsoft Word *.docx file!
ok... i am sending the VHD extension file... thanks for your concern really... regards
this is zip file, containing everything...
> .docx > .ise > .rar > zip I cannot help you with those files, because I'm on a smartphone and can't open either one of them... So just attach the according *.vhd or *.vhdl file. Is it that difficult?
ok... this is the file extension .vhd.. please sought out my problem.. problem is at the K_temp thanks regards
--error is here-"Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2 K_temp := "0100000000000000000000000000000000" /A ;
Oooops, a divider. Is this design for a FPGA? You can simulate a division easily. But if you want it to run on real hardware, you will get immediately into trouble, if the divisor isn't a power of 2 (like 2, 4, 8, 16, 32...). Because if the divisor is a power of 2, then the division is just a different wiring inside the FPGA. Thats easy, and its done by the synthesizer on its won. If the divisor is not a power of 2, then the division gets fairly complex. You then usually involve a divider-core, plus you will have to read a manual of at least 20 pages... :-o BTW:
Use IEEE .numeric_std .All ; -- take his one use IEEE.std_logic_signed.all; -- or those old osolete ones here --use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; -- but never all of them together!!!
-- *********************** --* Begin main process . * -- *********************** Begin Process ( z_position , reset ) Is
1. There is no "main process". Every process has the very same proirity, because every process will be synthesized to hardware. 2. The reset is absolutely unnecessary. Because even with reset='1' the reset-values of x and P will be overwritten immediately in the first two lines after the "end if;". BTW3:
x := ("00000000000000010000000000000000", "00000000000000010000000000000000");
For better readability try this:
x := (x"00010000",x"00010000");
x := (to_signed(65536,32),to_signed(65536,32));
BTW4: >>> Begin main process This whole design looks like you are "thinking in software", this will not lead to a solution for a language that "describes hardware"!
So what to do now? should i use ipcore? or one thing is in my mind, tell me is it possible in K_temp := "0100000000000000000000000000000000" /A ; first i convert "0100000000000000000000000000000000" into integer and then convert A into integer.. then divide both bcoz they are in integer now.. after that the resultant of the divison be converted back into signed... please help me out.. thanks best regards
> or one thing is in my mind, tell me is it possible .... > then divide both bcoz they are in integer now.. Absolutely NO. Because casting and converting does not change one thing at the fact: you want to do a division. You're tricking around and hoping for a hidden way. That will not work here... > should i use ipcore? I think you will have to. And: read ALL of the documentation.
thanks a lot.... i would go for ipcore..if i have any problem, i know who can help me now... best reagrds....
thanks... i have implemented the divisor core... the whole program is working well now... thanks a ton really.. regards...
> the whole program is working well now... Once more (the last time): you do not program a FPGA. You're writing a hardware description for a FPGA. > thanks a ton really.. You're welcome.
Yes... now implementing on FPGA... Regards...