Forum: FPGA, VHDL & Verilog Error when ran make file

von (unknown) (Guest)

Rate this post
0 useful
not useful
Hi.I written VHDL code once i ran my make file in GHDL simulator it 
gives below error.

ghdl1: fatal error: can’t open work/e~my file name.s for writing: No 
such file or directory

Thanks in advance


von Grey (Guest)

Rate this post
0 useful
not useful
the error is already mentioned: the file is missing or ghdl has no write 
access in this directory. do u checked this?

von (unknown) (Guest)

Rate this post
0 useful
not useful
Thanks for your replay.I checked and corrected my work directory.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.