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Forum: FPGA, VHDL & Verilog Failure: (vsim-3807) Types do not match between component and entity for port "out1".


Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von nd d. (Company: KPTM) (dee)

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Hi, i got error in model-sim altera,Failure: (vsim-3807) Types do not 
match between component and entity for port "out1". I got also failure 
for port out2 and so on.

When i check component in haar_tb.vhd : testbench file is same with 
entity in haar.vhd. Can I know what the solution for this problem.i got 
the error message when i click on EDA Gate Level simulation. please help 
me.

this haar.vhd:


LIBRARY ieee;
USE ieee.ALL;
ENTITY haar IS
PORT (
clock : IN bit;
-- Inputs
in1 : IN integer RANGE -127 TO 127;
in2 : IN integer RANGE -127 TO 127;
in3 : IN integer RANGE -127 TO 127;
in4 : IN integer RANGE -127 TO 127;
in5 : IN integer RANGE -127 TO 127;
in6 : IN integer RANGE -127 TO 127;
in7 : IN integer RANGE -127 TO 127;
in8 : IN integer RANGE -127 TO 127;
--Outputs
out1 : out integer RANGE -127 TO 127;
out2 : OUT integer RANGE -127 TO 127;
out3 : OUT integer RANGE -127 TO 127;
out4 : OUT integer RANGE -127 TO 127;
out5 : OUT integer RANGE -127 TO 127;
out6 : OUT integer RANGE -127 TO 127;
out7 : OUT integer RANGE -127 TO 127;
out8 : OUT integer RANGE -127 TO 127);
END haar;
ARCHITECTURE haar OF haar IS

COMPONENT reg

PORT (
input : IN integer RANGE -127 TO 127;
clock : IN bit;
output : Out integer RANGE -127 TO 127
);
END COMPONENT;
COMPONENT adddiv
PORT (
a : IN integer RANGE -127 TO 127;
b : in integer RANGE -127 TO 127;
clock : IN bit;
c : out integer RANGE -127 TO 127
);
END COMPONENT;
COMPONENT difference
PORT (
a : IN integer RANGE -127 TO 127;
b : in integer RANGE -127 TO 127;
clock : IN bit;
c : out integer RANGE -127 TO 127
);
END COMPONENT;
SIGNAL out_r1, out_r2, out_r3, out_r4, out_r5, out_r6, out_r7,
out_r8 : integer RANGE -127 TO 127;
SIGNAL out_a1, out_a2, out_a3, out_a4, out_a5, out_a6, out_a7,
out_a8 : integer RANGE -127 TO 127;
SIGNAL out_s1, out_s2, out_s3, out_s4, out_s5, out_s6, out_s7,
out_s8 : integer RANGE -127 TO 127;
SIGNAL clk : bit;
BEGIN
-- Input to Register here
r1: reg
PORT MAP ( in1, clock, out_r1 );
r2: reg

PORT MAP ( in2, clock, out_r2 );
r3: reg
PORT MAP ( in3, clock, out_r3 );
r4: reg
PORT MAP ( in4, clock, out_r4 );
r5: reg
PORT MAP ( in5, clock, out_r5 );
r6: reg
PORT MAP ( in6, clock, out_r6 );
r7: reg
PORT MAP ( in7, clock, out_r7 );
r8: reg
PORT MAP ( in8, clock, out_r8 );
-- Input to Add_Divide and Difference for stage 1
a1: adddiv
PORT MAP ( out_r1, out_r2, clock, out_a1 );
a2: adddiv
PORT MAP ( out_r3, out_r4, clock, out_a2 );
a3: adddiv
PORT MAP ( out_r5, out_r6, clock, out_a3 );
a4: adddiv
PORT MAP ( out_r7, out_r8, clock, out_a4 );
s1: difference
PORT MAP ( out_r1, out_r2, clock, out_s1 );
s2: difference
PORT MAP ( out_r3, out_r4, clock, out_s2 );
s3: difference
PORT MAP ( out_r5, out_r6, clock, out_s3 );
s4: difference
PORT MAP ( out_r7, out_r8, clock, out_s4 );
-- Input to AddDiv and Difference for stage 2
a5: adddiv
PORT MAP ( out_a1, out_a2, clock, out_a5 );
a6: adddiv
PORT MAP ( out_a3, out_a4, clock, out_a6 );
s5: difference
PORT MAP ( out_a1, out_a2, clock, out_s5 );
s6: difference
PORT MAP ( out_a3, out_a4, clock, out_s6 );
a7: adddiv
PORT MAP ( out_s1, out_s2, clock, out_a7 );
a8: adddiv
PORT MAP ( out_s3, out_s4, clock, out_a8 );
s7: difference
PORT MAP ( out_s1, out_s2, clock, out_s7 );
s8: difference
PORT MAP ( out_s3, out_s4, clock, out_s8 );
-- Input to AddDiv and Difference for stage 3
a9: adddiv
PORT MAP ( out_a5, out_a6, clock, out1 );
s9: difference
PORT MAP ( out_a5, out_a6, clock, out2 );
a10: adddiv
PORT MAP ( out_s5, out_s6, clock, out3 );
s10: difference
PORT MAP ( out_s5, out_s6, clock, out4 );
a11: adddiv
PORT MAP ( out_a7, out_a8, clock, out5 );
s11: difference
PORT MAP ( out_a7, out_a8, clock, out6 );
a12: adddiv
PORT MAP ( out_s7, out_s8, clock, out7 );
s12: difference
PORT MAP ( out_s7, out_s8, clock, out8 );
END haar;



this vhdl testbench haar_tb.vhd



-- Vhdl Test Bench template for design  :  haar
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;                                               
USE ieee.all;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;



ENTITY haar_tb IS
END haar_tb;
ARCHITECTURE haar_arch OF haar_tb IS
-- constants   
component haar
PORT (
clock : IN bit;
-- Inputs
in1 : IN integer RANGE -127 TO 127;
in2 : IN integer RANGE -127 TO 127;
in3 : IN integer RANGE -127 TO 127;
in4 : IN integer RANGE -127 TO 127;
in5 : IN integer RANGE -127 TO 127;
in6 : IN integer RANGE -127 TO 127;
in7 : IN integer RANGE -127 TO 127;
in8 : IN integer RANGE -127 TO 127;
--Outputs
out1 : out integer RANGE -127 TO 127;
out2 : OUT integer RANGE -127 TO 127;
out3 : OUT integer RANGE -127 TO 127;
out4 : OUT integer RANGE -127 TO 127;
out5 : OUT integer RANGE -127 TO 127;
out6 : OUT integer RANGE -127 TO 127;
out7 : OUT integer RANGE -127 TO 127;
out8 : OUT integer RANGE -127 TO 127);
 end component;





                                              
-- signals                                 

  signal clock: bit;
  signal in1: integer RANGE -127 TO 127;
  signal in2: integer RANGE -127 TO 127;
  signal in3: integer RANGE -127 TO 127;
  signal in4: integer RANGE -127 TO 127;
  signal in5: integer RANGE -127 TO 127;
  signal in6: integer RANGE -127 TO 127;
  signal in7: integer RANGE -127 TO 127;
  signal in8: integer RANGE -127 TO 127;
  signal out1: integer RANGE -127 TO 127;
  signal out2: integer RANGE -127 TO 127;
  signal out3: integer RANGE -127 TO 127;
  signal out4: integer RANGE -127 TO 127;
  signal out5: integer RANGE -127 TO 127;
  signal out6: integer RANGE -127 TO 127;
  signal out7: integer RANGE -127 TO 127;
  signal out8: integer RANGE -127 TO 127;




BEGIN
  uut : haar
  PORT MAP (
-- list connections between master ports and signals
  clock => clock,
  in1 => in1,
  in2 => in2,
  in3 => in3,
  in4 => in4,
  in5 => in5,
  in6 => in6,
  in7 => in7,
  in8 => in8,
  out1 => out1,
  out2 => out2,
  out3 => out3,
  out4 => out4,
  out5 => out5,
  out6 => out6,
  out7 => out7,
  out8 => out8
  );
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once     

clock<='0';
wAIT for 10 ns;
clock<='1'; 
wait for 10 ns;                                                    
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
in1<= 18;
in2<= 5;
in3<= 1;
in4<= 9;
in5<= 13;
in6<= 6;
in7<= 2;
in8<= 3;
  
WAIT for 50 ns; 
  
---------------------Second Test------------------
in1 <= 9;
in2 <= 2;
in3 <= 12;
in4 <= 5;
in5 <= 10;
in6 <= 60;
in7 <= 23;
in8 <= 13;
wait for 50ns;
---------------------Third Test--------------------
in1 <= 18;
in2 <= 52;
in3 <= 11;
in4 <= 1;
in5 <= 8;
in6 <= 61;
in7 <= 28;
in8 <= 77;
wait for 50ns;

wait;
END PROCESS always;                                          
END haar_arch;


configuration CFG_TB of haar_TB is 
for haar_arch 
end for; 
end CFG_TB;


Thank you.

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von Lothar M. (lkmiller) (Moderator)

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> Can I know what the solution for this problem
Try it this way: define a package with your constrained integer as a new 
(sub-)type. And then pass this "costumized" type on the port.

With a "customized" type you can also take advantage to write the 
complete code shorter and more generic.

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von nd d. (Company: KPTM) (dee)

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I create  1 file named haar_gate.vhd for gate implementation

do you mean like this code:
LIBRARY ieee;
USE ieee.ALL;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

package data_types is
subtype byte is integer range -127 to 127;
end data_types;


LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY haar_gate is

generic (byte : integer:= 8);

PORT (
clock : IN bit;
in1 ,in2,in3,in4,in5,in6,in7,in8: IN integer;
out1 ,out2,out3,out4,out5,out6,out7,out8: out integer);
END haar_gate;

ARCHITECTURE haar OF haar_gate IS
--as before
END haar;



But i got the same error.....
sorry, i'm beginner in vhdl code

Thanks for response

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von Lothar M. (lkmiller) (Moderator)

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Ok one step back. Try this simple design:
LIBRARY ieee;
USE ieee.ALL; -- seems to be a nice idea, 
              -- but beware of double type definitions!

entity intport is
    Port ( clk : in  bit;
           di  : in  integer RANGE -127 TO 127;
           do  : out integer RANGE -127 TO 127
          );
end intport;

architecture Behavioral of intport is

begin
   do <= di when (clk='1' and clk'event);
end Behavioral;


With this simple testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY tb_intport IS
END tb_intport;
 
ARCHITECTURE behavior OF tb_intport IS 
    COMPONENT intport
    PORT(  clk : IN  bit;
           di  : in  integer RANGE -127 TO 127;
           do  : out integer RANGE -127 TO 127);
    END COMPONENT;

   signal clk : bit := '0';
   signal di : integer range  -127 TO 127 := 0;
   signal do : integer range  -127 TO 127;
   signal s : signed(7 downto 0) := (others=>'0');

BEGIN
   uut: intport PORT MAP (
          clk => clk,
          di => di,
          do => do
        );

   clk <= not clk after 5 ns;
   s <= s+1 after 10 ns;
   di <= to_integer(s);
END;


What do you get as result? Is it working?

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von nd d. (Company: KPTM) (dee)

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yes, it is working.

when i click on EDA RTL simulation -  successful
the output as inport.jpg:
example
if di=0
when clk='1' and clk'event
do=0

di is input from 0 to 127
do is output (-127 when clk ='1' and clk'event ,the output is 0 to 127)
s =>s+1 after 10 ns (the binary of input).


when i click on EDA Gate level Simulation--i got error as the following:


# Reading C:/altera/11.1/modelsim_ase/tcl/vsim/pref.tcl
# do intport_run_msim_gate_vhdl.do
# if {[file exists gate_work]} {
#   vdel -lib gate_work -all
# }
# vlib gate_work
# vmap work gate_work
# Copying C:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to 
modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied 
C:\altera\11.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
#
# vcom -93 -work work {intport_2_1100mv_85c_slow.vho}
# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 
2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components
# -- Loading package std_logic_arith
# -- Loading package stratixiii_atom_pack
# -- Loading package stratixiii_components
# -- Compiling entity intport
# -- Compiling architecture structure of intport
#
# vcom -93 -work work {C:/Users/Public/Documents/learn/tb_intport.vhd}
# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 
2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity tb_intport
# -- Compiling architecture behavior of tb_intport
#
# vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp 
/uut=intport_2_1100mv_85c_vhd_slow.sdo -L altera -L stratixiii -L 
gate_work -L work -voptargs="+acc" tb_intport
# vsim +transport_int_delays +transport_path_delays -L altera -L 
stratixiii -L gate_work -L work -voptargs=\"+acc\" -sdftyp 
/uut=intport_2_1100mv_85c_vhd_slow.sdo -t 1ps tb_intport
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.tb_intport(behavior)
# SDF 10.0c Compiler 2011.09 Sep 21 2011
#
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading ieee.std_logic_arith(body)
# Loading stratixiii.stratixiii_atom_pack(body)
# Loading stratixiii.stratixiii_components
# Loading work.intport(structure)
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "clk".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 40
# Loading stratixiii.stratixiii_io_ibuf(arch)
# Loading stratixiii.stratixiii_io_obuf(arch)
# Loading stratixiii.stratixiii_clkena(vital_clkena)
# Loading stratixiii.stratixiii_ena_reg(behave)
# Loading stratixiii.stratixiii_and2(altvital)
# Loading stratixiii.stratixiii_lcell_comb(vital_lcell_comb)
# Loading altera.dffeas(vital_dffeas)
# Fatal error at intport_2_1100mv_85c_slow.vho line 40
#  while elaborating region: /tb_intport/uut
# Fatal error in file C:/Users/Public/Documents/learn/tb_intport.vhd
#  while elaborating region: /tb_intport
# Loading instances from intport_2_1100mv_85c_vhd_slow.sdo
# Loading timing data from intport_2_1100mv_85c_vhd_slow.sdo
# Load interrupted
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./intport_run_msim_gate_vhdl.do PAUSED at line 12

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von Lothar M. (lkmiller) (Moderator)

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> RTL simulation -  successful
Fine.
> Gate level Simulation
Who needs this?


However:
Give it a second try with
  USE ieee.std_logic_1164.ALL;
instead of
  USE ieee.ALL;
and std_logic instead of bit...

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von nd d. (Company: KPTM) (dee)

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Did you mean like this:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity intport is
    Port ( clk : in  bit;
           di  : in  integer RANGE -127 TO 127;
           do  : out integer RANGE -127 TO 127
          );
end intport;

architecture Behavioral of intport is

begin
   do <= di when (clk='1' and clk'event);
end Behavioral;


When Gate Level Simulation, i got same error:


# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "do".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 38
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "clk".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 39
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "di".
#    Time: 0 ps  Iteration: 0  Instance: /tb_intport/uut File: 
intport_2_1100mv_85c_slow.vho Line: 40


I got error in gate level simulation,is it effect when loading program 
into fpga?

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von Lothar M. (lkmiller) (Moderator)

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> I got error in gate level simulation,
Who needs a gate level simulation?
> is it effect when loading program into fpga?
Look at the synthesizer messages.
If you can't see any errors there, your design will run fine.

Look at this simple piece of codee:
signal cnt : integer range 0 to 15;
:
:
cnt <= cnt + 1 when rising_edge(clk);

For hardware synthesis this will result in a 4 bit counter.
But the simulation will lead to major problems when cnt reaches 15.

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von saba10 (Guest)

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hi ,
        i had the same problem.it was fine with the pre-synthesis 
simulation but i got the following error message when i tried a 
post-synthesis simulation ....

# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "fs1".
#    Time: 0 ps  Iteration: 0  Instance: /tb_afsk/uut File: 
C:/Actelprj/afsk/synthesis/afsk.vhd Line: 12
# ** Failure: (vsim-3807) Types do not match between component and 
entity for port "data_in".
#    Time: 0 ps  Iteration: 0  Instance: /tb_afsk/uut File: 
C:/Actelprj/afsk/synthesis/afsk.vhd Line: 13
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading proasic3.vtables
# Loading proasic3.or2(vital_act)
# Loading proasic3.xor2(vital_act)
# Loading proasic3.inbuf(vital_act)
# Loading proasic3.or2b(vital_act)
# Loading proasic3.or2a(vital_act)
# Loading proasic3.oa1b(vital_act)
# Loading proasic3.dfn1e0(vital_act)
# Loading proasic3.xnor2(vital_act)
# Loading proasic3.ax1a(vital_act)
# Loading proasic3.nor3a(vital_act)
# Loading proasic3.nor2b(vital_act)
# Loading proasic3.xa1(vital_act)
# Loading proasic3.ax1c(vital_act)
# Loading proasic3.ao1(vital_act)
# Loading proasic3.ao1c(vital_act)
# Loading proasic3.xnor3(vital_act)
# Loading proasic3.nor3c(vital_act)
# Loading proasic3.axo5(vital_act)
# Loading proasic3.dfn1e1c1(vital_act)
# Loading proasic3.axo1(vital_act)
# Loading proasic3.ax1b(vital_act)
# Loading proasic3.ao1b(vital_act)
# Loading proasic3.nor2a(vital_act)
# Loading proasic3.xa1a(vital_act)
# Loading proasic3.ax1(vital_act)
# Loading proasic3.aoi1b(vital_act)
# Loading proasic3.aoi1(vital_act)
# Loading proasic3.ax1e(vital_act)
# Loading proasic3.nor3(vital_act)
# Loading proasic3.xai1a(vital_act)
# Loading proasic3.ax1d(vital_act)
# Loading proasic3.oai1(vital_act)
# Loading proasic3.nor2(vital_act)
# Loading proasic3.oa1a(vital_act)
# Loading proasic3.oa1(vital_act)
# Loading proasic3.and2(vital_act)
# Loading proasic3.nor3b(vital_act)
# Loading proasic3.gnd(vital_act)
# Loading proasic3.outbuf(vital_act)
# Loading proasic3.vcc(vital_act)
# Loading proasic3.and3(vital_act)
# Loading proasic3.min3(vital_act)
# Loading proasic3.or3c(vital_act)
# Loading proasic3.axo2(vital_act)
# Loading proasic3.ao18(vital_act)
# Loading proasic3.mx2c(vital_act)
# Loading proasic3.mx2a(vital_act)
# Loading proasic3.xor3(vital_act)
# Loading proasic3.or3a(vital_act)
# Loading proasic3.clkbuf(vital_act)
# Loading proasic3.axoi1(vital_act)
# Loading proasic3.ao1d(vital_act)
# Loading proasic3.maj3(vital_act)
# Loading proasic3.mx2(vital_act)
# Loading proasic3.ao1a(vital_act)
# Loading proasic3.oa1c(vital_act)
# Loading proasic3.dfn1e0c1(vital_act)
# Fatal error at C:/Actelprj/afsk/synthesis/afsk.vhd line 13
#  while elaborating region: /tb_afsk/uut
# Fatal error in file C:/Actelprj/afsk/stimulus/tb_afsk.vhd
#  while elaborating region: /tb_afsk
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./run.do PAUSED at line 15

i would be very thankful if you can help me with solution for this 
problem ??

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Failure: (vsim-3807) Types do not match between component and entity for port "out1".
von bko (Guest)

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your synthesis must have generated a VHDL-netlist. Try to find
this netlist - open it in an editor, then look
for the porttypes of your desin toplevel ...

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