In one of my class I have to program a latch with VHDL without using
processes, functions etc. So I made the first latch, simulated it, and
it worked. But for the flip-flop, I have to put two latches together,
one master and one slave, everything seems to work when I compile but as
soon as I simulate I get this error.
# KERNEL: Delta count overflow - stopped. Try to increase the iterations
limit in simulator preferences.
# Fatal error occurred during simulation.
I'm using Active-HDL 8.3 by the way. As far as I know, this happens when
you have an infinite loop, or something like that, and in my code, I
think the problem is with the clock I'm using, here's the code:
library IEEE;
use IEEE.std_logic_1164.all;
entity latch is
port(
clk : in std_logic; -- signal reset
D : in std_logic; -- donnee en entree
Q : out std_logic; -- donnee en sortie
notQ : out std_logic -- valeur complement
);
end latch;
architecture latch_arch of latch is
signal DN, SN, RN, IQ, IQN : std_logic;
begin
DN <= not D;
SN <= clk nand D;
IQ <= SN nand IQN;
IQN <= DN nand IQ;
Q <= IQ;
notQ <= IQN;
end latch_arch;
-----------End for the flip-flop that uses the latch I just made
library IEEE;
use IEEE.std_logic_1164.all;
use LABO44.latch;
entity flipflop is
port(
clk : in std_logic; -- signal d'horloge
D : in std_logic; -- donnee en entree
Q : out std_logic; -- donnee en sortie
notQ : out std_logic -- valeur complement
);
end flipflop;
architecture flipflop_arch of flipflop is
signal Din, CN, Qm, QmN, Qs, QsN :std_logic ;
component latch
port (clk, D: in std_logic; Q, notQ : out std_logic ); end component;
begin
Din <= D;
CN <= not clk;
U1: latch port map (CN, Din, Qm, QmN);
U2: latch port map (clk, Qm, Qs, QsN);
Q<=Qs; notQ<=QsN;
end flipflop_arch;
I don't really know what to do with this, It must be a pretty stupid
error so, any help? Thanks a lot!