hello at everybody I'm trying to start to do some test with a Xilinx ML605 Evaluation Board, making use of a FPGA Virtex 6 core. I would map a very simple algorithm to fpga at the beginning (like a counter for example), but I have some communication problems with the board. I don't know what port I can use and how to estabilish the connection. Can you help me with some simple examples? thank you all
A very unspecific question. Maybe just take a look in an actual FPGA-Book e.g. "VHDL 101: Everything you need to know to get started" by William Kafig. Or you can try some delivered examples... Duke
sorry I will try to specify my problem I have done the verification of the board's functionality as reported in "Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit" (pag 1 to 27) but I didn't test the board by PCI Express because I have a laptop. Now I would know if I can map and synthetize a simple project (I am able to create it in vhdl by myself) by the JTAG Cable Connector. Have I install some driver or somthing like that to estabilish the connection? I've used a spartan 3a fpga and I had not problem to synthetize and map a simple project with the usb cable and the ISE design tool but with this board I don't succeed. Thanks a lot for the reply.