Hi, I face a problem when I try to force a signal in my Verilog testbench My v file is: module test(I); input I; wire tmp; wire NB; assign NB = I; assign tmp = NB; endmodule My testbench is: module tb(); reg in; test test(in); initial begin in = 1; #10; force tb.test.I = 1'b0; #20; release tb.test.I; #20; $finish; end //initial endmodule // tb_scu When I look at the simu result, signal I is following my force/release but NB (and therefore tmp) is not. I am really unable to figure out the problem. Does anyone see something wrong or have an idea? Tahnks a lot. Br
Bruno, in case this works test test(in); initial begin in = 1; #10; in = 0; #20; in = 1; #20; $finish; end //initial I also would assume that this is a simulator issue. I don't see any reason why the forced value should not be propagated through the assign statement. What simulator are you using? Harald
Thanks for your answer. Yes your piece of code works. I was using iverilog, I tried with cver, it works now. Then it is a icarus verilog simulator related issue. Thanks a lot fo your help !
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