Hi,
I face a problem when I try to force a signal in my Verilog testbench
My v file is:
module test(I);
input I;
wire tmp;
wire NB;
assign NB = I;
assign tmp = NB;
endmodule
My testbench is:
module tb();
reg in;
test test(in);
initial begin
in = 1;
#10;
force tb.test.I = 1'b0;
#20;
release tb.test.I;
#20;
$finish;
end //initial
endmodule // tb_scu
When I look at the simu result, signal I is following my force/release
but NB (and therefore tmp) is not.
I am really unable to figure out the problem.
Does anyone see something wrong or have an idea?
Tahnks a lot.
Br