I face a problem when I try to force a signal in my Verilog testbench
My v file is:
assign NB = I;
assign tmp = NB;
My testbench is:
in = 1;
force tb.test.I = 1'b0;
endmodule // tb_scu
When I look at the simu result, signal I is following my force/release
but NB (and therefore tmp) is not.
I am really unable to figure out the problem.
Does anyone see something wrong or have an idea?
Tahnks a lot.