Hi, I was just wondering how it would be possible to make an all purpose sign extension entity in VHDL. So I created this sign extension entity but it will only work if the input is 6 bits long. If I put in an input that was say 3 bits long. It wouldn't work. Is it possible to build a SEXT that doesn't have limitation on input bits? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SEXT5_0 is port ( data_in : in std_logic_vector(5 downto 0); data_out : out std_logic_vector(15 downto 0)); end SEXT5_0; architecture behavioral of SEXT5_0 is begin process (Input) begin data_out(5 downto 0) <= data_in; data_out(15 downto 16) <= (15 downto 6 => data_in(5)); end process; end behavioral;
> Is it possible to build a SEXT that doesn't have limitation on input bits?
Take the numeric_std package instead of the old and obsolete
STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED. And then simply write:
1 | data_out <= std_logic_vector(resize(unsigned(data_in),data_out'width)); |
If you want to make your solution more generic then write it this way:
1 | data_out(data_in'range) <= data_in; |
2 | data_out(data_out'left downto data_in'width) <= (data_out'left downto data_in'width => data_in(data_in'left)); |
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