In VHDL, variable should make no delay between value assignment. But how
about mix signal and variables? In code below, X and Y are variables and
Z is output. Why the delay between Z and input A,B is 3 clocks? Why it's
not 1 clock delay?
Thanks in advance.
==========================
process(clk)
variable X,Y:std_logic;
begin
if(clk's event and clk='1') then
Z<=Y;
Y:=X;
X:=A and B;
end if;
end process;
> Why it's not 1 clock delay? Becuase the variables are read before they are written, therefore they must be storing. > Why the delay between Z and input A,B is 3 clocks? Its not called delay, its latency... Play "FPGA" and do the process on your own:
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The two AFTER THAT are the two additional clock cycles... If you would turn it around ther would be no additional latency:
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Because then the variables are not storing...
Guest
#2377265
- Variables are assignmed sequentially, so order of assignment matters - Signals are assigned "all together" at the end of a time tick so this is what happens after input A or B changes: 1st clock event Z is marked not to change, as variable Y has still the old value Y is assigned the old value of X (as it has not changed so far) X is assigned the new "A and B" 2nd clock event Z is marked not to change, as variable Y has still the old value Y is assigned the value of X as from 1st clock event X is assigned the new "A and B" 3rd clock event Z is marked to get the value of Y at the end of the process Y is assigned the value of X as from 2nd clock event X is assigned the new "A and B" Z is assigned the value of Y Here we are...
Very clear clarification. Thank you all very much!
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