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VHDL Project with Verilog IP
von John Douglas (Guest)

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Hi there,

I have a project in VHDL and I want to buy some IP from Synopsys but the 
IP is written in Verilog.

Would I be able to use it in the project and synthesize it?

Thank you.

Regards,
John

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Re: VHDL Project with Verilog IP
von user (Guest)

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It is possible, for FPGAs Xilinx and Altera allow a mixed synthesis 
(VHDL / Verilog)

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Re: VHDL Project with Verilog IP
von John (Guest)

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Thanks a lot.

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