Hey everyone,
I've got a hopefully easy to solve question.
The following Code is given:
1 | module filter
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2 | (
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3 | input clk,
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4 | input en,
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5 | input [31:0] rawdata,
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6 | output [31:0] filtered_data
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7 | );
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8 |
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9 | reg [31:0] filtered_data_q;
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10 |
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11 | assign filtered_data = filtered_data_q;
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12 |
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13 | // filter + register
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14 | always @(posedge clk)
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15 | if (en)
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16 | // Simple recursive filtering
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17 | filtered_data_q <= filtered_data_q * 3 / 4 + rawdata / 4;
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18 | else
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19 | filtered_data_q <= filtered_data_q;
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20 |
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21 | endmodule
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This code synthesizes and simulates perfectly, just as expected.
But once I add a simple(st) buffer, nothing works:
1 | wire temp;
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2 | assign temp = rawdata;
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Additionally, I used 'temp' instead of 'rawdata' for the filter.
The result is that my complete filtered_q register is removed during
optimization step for the following reason: "Stuck at GND due to stuck
port data_in"
I also tried
1 | reg temp;
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2 | always @ (rawdata)
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3 | temp = rawdata;
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but that did not change anything.
Any Explanations? Why does this happen?