EmbDev.net

Forum: FPGA, VHDL & Verilog how to include verilogCSP macros in standard verilog


how to include verilogCSP macros in standard verilog
von vidhya a. (Company: student) (vidhya)

Attached files:
Rate this post
0 ▲ useful
▼ not useful 
hi

i'm in need to design a asynchronous router using verilogCSP.... To use 
this language i need to include some macros in standard verilog if i 
include this macros file using `include i'm getting error in tne macros 
file itself... here i'm attaching the macros file that is to be 
included... pls give me some suggestion how the macros can be included

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.