Hi, I'm getting back into hardware design after a long absence (last programmed PALs with PALASM). I'm considering playing with Terasic's DE0-Nano and have obtained Altera's Quartus software. So - now there is a new language to learn Is there an advantage of Verilog over VHDL? Any thoughts, experiences would be greatly appreciated. Regards Marc
Largely personal preference. Each has advantages and disadvantages. However, both will get the job done in most cases. I prefer Verilog. It is much easier to learn and read. I'm a stickler for code consistency/readability, though. Much of the Verilog syntax is similar to C.
Depends mainly on the region you work/want to work. I also started with verilog because the terasic de1 has all examples in verilog only. But noone i know has even little experience in verilog and all is done in vhdl so i had to switch over. Both have advantages and you should at least understand both in far future.
Thanks abc I have come to the same conclusion, learn both :) what sort of projects have you worked on? regards Marc