help with SPI slave implementation in Verilog

I am working an embedded system where I have a micro-controller as the 
SPI master and an Altera Max II CPLD as the SPI slave.  My slave 
peripheral works correctly most of the time but every once in a while 
the data is 1 bit off always in the same direction (ie. I expect a 2, 
and get a 1):

The  CPLD clock is 2.048 MHz, SPI_SCK is 100 KHz

Any help is greatly appreciated!

always @(posedge OSC2048MHz)
        // SPI_SEL must be low to talk SPI
        if(!SPI_SEL)
        begin
           case(SPI_state)
              0:      // load the shift register
              begin
                // if there is data in the FIFO, load into shift 
register
                if(!FIFO_empty)
                    begin
                       SPI_sr  <= FIFO_rd_bus;
                       FIFO_rd <= 1;
                    end
                else
                    // if the FIFO is empty, load the status
                    begin
                       PI_sr <= stat;
                    end

                    SPI_state <= 2'd1;
             end
            1:   // wait for SPI_SCK to go high
            begin
               if(SPI_SCK)
                    begin
                       SPI_MISO <= SPI_sr[SPI_sr_bits-1];
                       SPI_sr[SPI_sr_bits-1:1] <= 
SPI_sr[SPI_sr_bits-2:0];
                       SPI_state <= 2'd2;
                    end
            end
            2:      // wait for SPI_SCK to go low
            begin
               if(!SPI_SCK)
                  SPI_state <= 2'd1;
            end
            3:      // should never get here
            begin
                SPI_state <= 2'd0;
            end
        endcase
    end
    else  // if SPI_SEL is high, reset the state machine bring the MISO 
line low
    begin
            SPI_MISO  <= 1'b0;
            SPI_state <= 2'd0;
    end
    if(FIFO_rd)
        FIFO_rd <= 0;
end