[VHDL] Beginner: "Syntax error near use "

John E. OP #2301294
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Hello All,

As a beginner, I am trying to simulate an XOR gate using AND gates and 
OR gate that I created in vhdl modules and_gate and or_gate 
respectively.

I have a syntax error ("Syntax error near use") on line 62  (marked 
"--Error--") of the testbench file which I am unable to resolve.

Can anyone spot the mistake?

TESTBENCH FILE
---------------

Here is the code:
--X--

1
entity tb_xor_gate is

2
end tb_xor_gate;

3


4
architecture Behavioral of tb_xor_gate is

5
  component xor_gate

6
    port (output: out bit; 

7
        input_a, input_b: in bit);

8
  end component;

9
  

10
  signal signal_a, signal_b, output: bit;

11
begin

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  XG1: xor_gate port map (input_a => signal_a, input_b => signal_b, 

13
                  output => output);

14
  

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  DUT: process

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    begin

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    signal_a <= '0'; signal_b <= '0';

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    wait for 10 ns;

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    signal_a <= '0'; signal_b <= '1';

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    wait for 10 ns;

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    signal_a <= '1'; signal_b <= '0';

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    wait for 10 ns;

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    signal_a <= '1'; signal_b <= '1';

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    wait for 10 ns;

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  end process DUT;

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end Behavioral;

27


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configuration cfg_tb_xor_gate of tb_xor_gate is

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  for Behavioral

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    for DUT:

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      use entity work.xor_gate(Behavioral2); --Error--

32
    end for;

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  end for;

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end cfg_tb_xor_gate;

--X--

Here is my .vhd File for xor_gate that compiles successfully. The AND 
gates and OR gates also compile without any issues.
--X--
1
entity xor_gate is

2
  port(output: out bit; 

3
      input_a, input_b: in bit);

4
end xor_gate;

5


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architecture Behavioral2 of xor_gate is

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  component or_gate 

8
    port (output: out bit; 

9
        input_a, input_b: in bit);

10
  end component;

11
  

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  component and_gate 

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    port (output: out bit; 

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        input_a, input_b: in bit);

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  end component;

16
  

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  signal a_not_b, b_not_a: bit;

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  signal not_inp_a, not_inp_b: bit;

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begin

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  not_inp_a <= not input_a;

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  not_inp_b <= not input_b;

22
  

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  G1: and_gate port map(a_not_b, input_a, not_inp_b);

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  G2: and_gate port map(b_not_a, input_b, not_inp_a);

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  G3: or_gate port map(output, a_not_b, b_not_a);

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end Behavioral2;

27


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configuration cfg_xor_gate of xor_gate is

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  for Behavioral2

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    for G1: and_gate

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      use entity work.and_gate(Behavioral);

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    end for;

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    for G2: and_gate 

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      use entity work.and_gate(Behavioral);

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    end for;

37
    

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    for G3: or_gate

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      use entity work.or_gate(Behavioral);

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    end for;

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  end for;

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end configuration;

--X--

Thanks
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John E. OP #2302756
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Hello All,

I spotted the mistake.

The "configuration" block in test bench is completely wrong. I am trying 
to assign a configuration of an xor gate for an xor gate used in block 
DUT.

But DUT is a process in testbench with no xor gate. Hence, I retyped the 
configuration block in the testbench file as:

------------------------------------------------
1
configuration cfg_tb_xor_gate of tb_xor_gate is

2
  for Behavioral

3
    for XG1:xor_gate

4
      use entity work.xor_gate(Behavioral2);

5
    end for;

6
  end for;

7
end cfg_tb_xor_gate;

------------------------------------------------

The code now compiles.

Regards,

Edwards
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